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參數(shù)資料
| 型號(hào)： | ADC12181EVAL |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 5 MHz Self-Calibrating, Pipelined A/D Converter |
| 中文描述： | 12位，5兆赫自校準(zhǔn)，流水線A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 322K |
| 代理商： | ADC12181EVAL |
Applications Information
(Continued)
should be avoided as even a little coupling can cause prob-
lems at high frequencies. This is because other lines can
introduce phase noise (jitter) into the clock line, which can
lead to degradation of SNR.
Best performance at high frequencies and at high resolution
is obtained with a straight signal path. That is, the signal path
through all components should form a straight line wherever
possible.
Be especially careful with the layout of inductors. Mutual
inductance can change the characteristics of the circuit in
which they are used. Inductors should not be placed side by
side, even with just a small part of their bodies beside each
other.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. Any
external component (e.g., a filter capacitor) connected be-
tween the converter’s input and ground should be connected
to a very clean point in the analog ground plane.
Figure 6
gives an example of a suitable layout. All analog
circuitry (input amplifiers, filters, reference components, etc.)
should be placed on or over the analog ground plane. All
digital circuitry and I/O lines should be placed over the digital
ground plane.
All ground connections should have a low inductance path to
ground.
6.0 LAYOUT AND GROUNDING
The ADC12181 can achieve impressive dynamic perfor-
mance. To achieve the best dynamic performance with the
ADC12181, the clock source driving the CLK input must be
free of jitter. For best ac performance, isolating the ADC
clock from any digital circuitry should be done with adequate
buffers, as with a clock tree. See
Figure 7
.
It is good practice to keep the ADC clock line as short as
possible and to keep it well away from any other signals.
Other signals can introduce phase noise (jitter) into the clock
signal, which can lead to increased distortion. Even lines
with 90 crossings have capacitive coupling, so try to avoid
even these 90 crossings of the clock line.
10103924
FIGURE 6. Layout example
10103925
FIGURE 7. Isolating the ADC clock from other circuitry
with a clock tree.
A
www.national.com
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