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參數(shù)資料
| 型號(hào)： | ADC121S101EVAL |
| 廠商： | National Semiconductor Corporation |
| 元件分類(lèi)： | 串行ADC |
| 英文描述： | 1MSPS, 12-/10-/8-Bit A/D Converters in SOT-23 |
| 中文描述： | 1MSPS，12/10/8位的A / D轉(zhuǎn)換器采用SOT - 23 |
| 文件頁(yè)數(shù)： | 15/20頁(yè) |
| 文件大?。?/td> | 1049K |
| 代理商： | ADC121S101EVAL |
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Functional Description
TheADC121S625 analog-to-digital converter uses a succes-
sive approximation register (SAR) architecture based upon
capacitive redistribution containing an inherent sample/hold
function.
The
architecture
ADC121S625 to acquire and convert an analog signal at
sample rates up to 200,000 conversions per second while
consuming very little power.
The ADC121S625 requires an external reference and exter-
nal clock, and a single +5V power source that can be as low
as +4.5V. The external reference can be any voltage be-
tween 100mV and 2.5V. The value of the reference voltage
determines the range of the analog input, while the reference
input current depends on the conversion rate.
The external clock can take on values as indicated in the
Electrical Characteristics Table of this data sheet. The duty
cycle of the clock is essentially unimportant, provided the
minimum clock high and low times are met. The minimum
clock frequency is set by internal capacitor leakage. Each
conversion requires 16 SCLK cycles to complete. Short
cycling can reduce this to 14 or 15 SCLK cycles, depending
upon whether the clock edge after the fall of CS is a rise or
a fall. See the timing diagrams.
The analog input is presented to the two input pins: +IN and
–IN. Upon initiation of a conversion, the differential input at
these pins is sampled on the internal capacitor array. The
inputs are disconnected from internal circuitry while a con-
version is in progress.
The digital conversion result is clocked out by the SCLK
input and is provided serially, most significant bit first, at the
D
pin. The digital data that is provided at the D
pin is
that of the conversion currently in progress. It is possible to
continue to clock the ADC121S625 after the conversion is
complete and to obtain the serial data least significant bit
first. Each bit of the data word (including the leading null bit)
is clocked out on subsequent falling edges of SCLK and can
be clocked into the receiving device on the rising edges. See
the Digital Interface section and timing diagram for more
information.
and
process
allow
the
1.0 REFERENCE INPUT
The externally supplied reference voltage sets the analog
input range. The ADC121S625 will operate with a reference
voltage in the range of 100mV to 2.5V. However, care must
be exercised when the reference voltage is less than 500
millivolts.
As the reference voltage is reduced, the range of input
voltages corresponding to each digital output code is re-
duced. That is, a smaller analog input range corresponds to
one LSB (Least Significant Bit). The size of one LSB is equal
to twice the reference voltage divided by 4096. When the
LSB size goes below the noise floor of theADC121S625, the
noise will span an increasing number of codes and overall
noise performance will suffer. That is, for dynamic signals the
SNR will degrade and for d.c. measurements the code un-
certainty will increase. Since the noise is Gaussian in nature,
the effects of this noise can be reduced by averaging the
results of a number of consecutive conversions.
Additionally, since offset and gain errors are specified in
LSB, any offset and/or gain errors inherent in the A/D con-
verter will increase in terms of LSB size as the reference
voltage is reduced.
The ADC121S625 is more sensitive to nearby signals and
EMI (electromagnetic interference) when a low reference
voltage is used. For this reason, extra care should be exer-
cised in planning a clean layout, a low noise reference and a
clean power supply when using low reference voltages.
The reference input and the analog inputs are connected to
the capacitor array through a switch matrix when the input is
sampled. Hence, the only current required at the reference
and at the analog inputs is only a series of transient spikes.
The amount of these current spikes will depend, to some
degree, upon the conversion code, but will not vary a great
deal.
The current required to recharge the input capacitance at the
reference and analog signal inputs will cause voltage spikes
at these pins. Do not try to filter our these noise spikes.
Rather, ensure that the transient settles out during the
sample period (1.5 clock cycles after the fall at the CS input).
Lower reference voltages will decrease the current pulses at
the reference input and, therefore, will slightly decrease the
average input current there because the internal capaci-
tance is required to take on a lower charge at lower refer-
ence voltages. The reference current changes only slightly
with temperature. See the curves, “Reference Current vs.
Sample Rate”, “Reference Current vs. Temperature” and
“SNR vs. V
REF
” in the Typical Performance Curves section.
2.0 ANALOG SIGNAL INPUTS
The ADC121S625 has a differential input. As such, the ef-
fective input voltage that is digitized is (+IN) (IN).As is the
case with any differential input A/D converter, operation with
a fully differential input signal or voltage will provide better
performance than with a single-ended input. Yet, the
ADC121S625 can be presented with a single-ended input.
2.1 Differential Input Operation
With a fully differential input voltage or signal, a positive full
scale output code (0111 1111 1111b or 7FFh) will be obtained
when (+IN) (IN)
≥
V
REF
1.5 LSB and a negative full
scale code (1000 0000 0000b or 800h) will be obtained when
(+IN) (IN)
≤
V
REF
+ 0.5 LSB. This ignores gain, offset
and linearity errors, which will affect the exact differential
input voltage that will determine any given output code.
2.2 Single-Ended Input Operation
For single-ended operation, the non-inverting input (+IN) of
the ADC121S625 should be driven with a signal or voltages
that have a maximum to minimum value range that is equal
to or less than twice the reference voltage. The inverting
input (IN) should be biased to a stable voltage that is half
way between these maximum and minimum values. Note
that single-ended operation should only be used if the per-
formance degradation (compared with differential operation)
is acceptable.
2.3 Input Common Mode Voltage
The allowable input common mode voltage (V
) range
depends upon the supply and reference voltages used for
the ADC121S625 and are depicted in
Figure 1
and
Figure 2
.
The minimum and maximum common mode voltages for
differential and single-ended operation are shown in
Table 1
.
A
www.national.com
15
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| ADC121S101EVM | 功能描述:EVAL BOARD FOR ADC121S101 制造商:texas instruments 系列:- 零件狀態(tài):在售 A/D 轉(zhuǎn)換器數(shù):1 位數(shù):12 采樣率（每秒）:1M 數(shù)據(jù)接口:串行 輸入范圍:0 ~ 5.25 V 不同條件下的功率（典型值）:10mW @ 1MSPS 使用的 IC/零件:ADC121S101 所含物品:板 標(biāo)準(zhǔn)包裝:1 |
| ADC121S101-Q1 | 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:Single Channel, 0.5 to 1 Msps, 12-Bit A/D Converter |
| ADC121S101QIMF/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Auto Sgl CH 0.5 to 1Msps 12B A/D Cnvtr RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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