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參數(shù)資料
| 型號： | ADC1230 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 自校準(zhǔn)12位帶符號串行I /辦公自動化/ D轉(zhuǎn)換器MUX和采樣/保持 |
| 文件頁數(shù)： | 31/41頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | ADC1230 |
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Application Hints
(Continued)
The Multiplexer assignment tables for the ADC12030,2,4,8
(Tables 2, 3, 4) summarize the aforementioned functions for
the different versions of A/Ds.
2.1 Biasing for Various Multiplexer Configurations
Figure 11 is an example of biasing the device for
single-ended operation. The sign bit is always low. The digi-
tal output range is 0 0000 0000 0000 to 0 1111 1111 1111.
One LSB is equal to 1 mV (4.1V/4096 LSBs).
For pseudo-differential signed operation, the biasing circuit
shown in Figure 12 shows a signal AC coupled to the ADC.
This gives a digital output range of 4096 to +4095. With a
2.5V reference, as shown, 1 LSB is equal to 610 μV. Al-
though, the ADC is not production tested with a 2.5V refer-
ence, linearity error typically will not change more than 0.1
LSB (see the curves in the Typical Electrical Characteristics
Section). With the ADC set to an acquisition time of 10 clock
periods, the input biasing resistor needs to be 600
or less.
Notice though that the input coupling capacitor needs to be
made fairly large to bring down the high pass corner. In-
creasing the acquisition time to 34 clock periods (with a
5 MHz CCLK frequency) would allow the 600
to increase to
6k, which with a 1 μF coupling capacitor would set the high
pass corner at 26 Hz. Increasing R, to 6k would allow R
2
to
be 2k.
Differential
Configuration
DS011354-40
A/DIN1 and A/DIN2 can be assigned as the + or input
Single-Ended
Configuration
DS011354-41
A/DIN1 is + input
A/DIN2 is input
FIGURE 10.
DS011354-46
FIGURE 11. Single-Ended Biasing
www.national.com
31
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