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參數(shù)資料
| 型號： | ADC1230 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 自校準12位帶符號串行I /辦公自動化/ D轉(zhuǎn)換器MUX和采樣/保持 |
| 文件頁數(shù)： | 9/41頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | ADC1230 |
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AC Electrical Characteristics
(Continued)
The following specifications apply for V
+
= V
+ = V
+ = +5.0 V
, V
+ = +4.096 V
, V
= 0 V
, 12-bit + sign conver-
sion mode, t
= t
= 3 ns, f
= f
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
= 25
, source impedance for V
+ and V
≤
25
,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
) acquisition time unless otherwise specified.
Bold-
face limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
ADC12H030/2/4/8
Limits
(Note 11)
4944(t
CK
)
618.0
76(t
CK
)
9.5
2(t
CK
)
3(t
CK
)
0.250
0.375
9(t
SK
)
1.125
ADC12030/2/4/8
Limits
(Note 11)
4944(t
CK
)
988.8
76(t
CK
)
15.2
2(t
CK
)
3(t
CK
)
0.40
0.60
9(t
SK
)
1.8
Units
(Limits)
t
CKAL
Self-Calibration Time
4944(t
CK
)
(max)
μs (max)
(max)
μs (max)
(min)
(max)
μs (min)
μs (max)
(max)
μs (max)
t
AZ
Auto-Zero Time
76(t
CK
)
t
SYNC
Self-Calibration
or Auto-Zero
Synchronization Time
from DOR
DOR High Time
when CS is Low
Continuously for Read
Data and Software
Power Up/Down
CONV Valid Data Time
2(t
CK
)
t
DOR
9(t
SK
)
t
CONV
8(t
SK
)
8(t
SK
)
1.0
8(t
SK
)
1.6
(max)
μs (max)
AC Electrical Characteristics
The following specifications apply for V
+
= V
+ = V
+ = +5.0 V
, V
+ = +4.096 V
, V
= 0 V
, 12-bit + sign conver-
sion mode, t
= t
= 3 ns, f
= f
= 8 MHz for the ADC12H030, ADC12H032, ADC12H034 and ADC12H038, f
CK
= f
SK
= 5
MHz for the ADC12030, ADC12032, ADC12034 and ADC12038, R
= 25
, source impedance for V
+ and V
≤
25
,
fully-differential input with fixed 2.048V common-mode voltage, and 10(t
) acquisition time unless otherwise specified.
Bold-
face limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= 25C. (Note 17)
Symbol
Parameter
Conditions
Typical
(Note 10)
140
Limits
(Note 11)
250
Units
(Limits)
μs (max)
t
HPU
Hardware Power-Up Time, Time from
PD Falling Edge to EOC Rising Edge
Software Power-Up Time, Time from
Serial Data Clock Falling Edge to
EOC Rising Edge
Access Time Delay from
CS Falling Edge to DO Data Valid
Set-Up Time of CS Falling Edge to
Serial Data Clock Rising Edge
Delay from SCLK Falling
Edge to CS Falling Edge
Delay from CS Rising Edge to
DO TRI-STATE
DI Hold Time from Serial Data
Clock Rising Edge
DI Set-Up Time from Serial Data
Clock Rising Edge
DO Hold Time from Serial Data
Clock Falling Edge
Delay from Serial Data Clock
Falling Edge to DO Data Valid
t
SPU
140
250
μs (max)
t
ACC
20
50
ns (max)
t
SET-UP
30
ns (min)
t
DELAY
0
5
ns (min)
t
1H
, t
0H
R
L
= 3k, C
L
= 100 pF
40
100
ns (max)
t
HDI
5
15
ns (min)
t
SDI
5
10
ns (min)
t
HDO
R
L
= 3k, C
L
= 100 pF
25
50
5
50
ns (max)
ns (min)
ns (max)
t
DDO
35
www.national.com
9
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