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參數(shù)資料
| 型號(hào)： | ADC12451 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold(可自行校對的12位帶采樣和保持功能的A/D轉(zhuǎn)換器) |
| 中文描述： | 動(dòng)態(tài)息審查自校準(zhǔn)12位帶符號(hào)的A / D轉(zhuǎn)換器采樣和保持（可自行校對的12位帶采樣和保持功能的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 311K |
| 代理商： | ADC12451 |
Electrical Characteristics
(Continued)
Note 7:
A diode exists between AV
CC
and DV
CC
as shown below.
TL/H/11025–5
To guarantee accuracy, it is required that the AV
CC
and DV
CC
be connected together to a power supply with separate bypass filters at each V
CC
pin.
Note 8:
Accuracy is guaranteed at f
CLK
e
3.5 MHz. At higher or lower clock frequencies accuracy may degrade, see the typical performance characteristic curves.
Note 9:
Typicals are at T
J
e
25
§
C and represent most likely parametric norm.
Note 10:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11:
Positive linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive full scale and
zero. For negative linearity error the straight line passes through negative full scale and zero. (See Figures 1b and 1c).
Note 12:
The ADC12451’s self-calibration technique ensures linearity, full scale, and offset errors as specified, but noise inherent in the self-calibration process will
result in a repeatability uncertainty of
g
0.20 LSB.
Note 13:
If T
A
changes then an Auto-Zero or Auto-Cal cycle will have to be re-started, see the typical performance characteristic curves.
Note 14:
After an Auto-Zero or Auto-Cal cycle at the specified power supply extremes.
Note 15:
When using the WR control to start a conversion if the clock is asynchronous to the rising edge of WR an uncertainty of one clock period will exist in the
end of the interval of t
A
, therefore making t
A
end a minimum 6 clock periods or a maximum 7 clock periods after the rising edge of WR. If the falling edge of the
clock is synchronous to the rising edge of WR then t
A
will end exactly 6.5 clock periods after the rising edge of WR. This does not occur when S/H control is used.
Note 16:
The CAL line must be high before a conversion is started.
Note 17:
The specifications for these parameters are valid after an Auto-Cal cycle has been completed.
Note 18:
The ADC12451 reference ladder is composed solely of capacitors.
Note 19:
A military RETS electrical test specification is available on request. At time of printing, the ADC12451CMJ/883 RETS specification complies fully with the
boldface
limits in this column.
TL/H/11025–6
FIGURE 1a. Transfer Characteristic
6
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC12451883 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| ADC12451CIJ | 功能描述:IC ADC 12BIT DYNAM TEST 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| ADC12451CMJ | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dynamically-Tested Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold |
| ADC12451CMJ/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog-to-Digital Converter， 13-Bit |
| ADC-12-4-75 | 制造商:MINI 制造商全稱:Mini-Circuits 功能描述:Directional Coupler 75Ω 20 to 1000 MHz |
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