參數(shù)資料
型號: ADC1251
廠商: National Semiconductor Corporation
英文描述: Self-Calibrating 12-Bit Plus Sign A/D Converter with Sample-and-Hold
中文描述: 自校準(zhǔn)12位帶符號的A / D轉(zhuǎn)換器的采樣保持電路
文件頁數(shù): 2/16頁
文件大小: 301K
代理商: ADC1251
Absolute Maximum Ratings
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
e
DV
CC
e
AV
CC
)
Negative Supply Voltage (V
b
)
6.5V
b
6.5V
Voltage at Logic Control Inputs
b
0.3V to (V
CC
a
0.3V)
Voltage at Analog Inputs
(V
REF
, V
IN
)
AV
CC
-DV
CC
(Note 7)
Input Current at Any Pin (Note 3)
(V
b
b
0.3V) to (V
CC
a
0.3V)
0.3V
g
5 mA
g
20 mA
875 mW
Package Input Current (Note 3)
Power Dissipation at 25
§
C (Note 4)
Storage Temperature Range
b
65
§
C to
a
150
§
C
ESD Susceptability (Note 5)
2000V
Soldering Information
J Package (10 sec.)
300
§
C
Operating Ratings
(Notes 1 & 2)
Temperature Range
ADC1251BIJ, ADC1251CIJ
ADC1251CMJ
ADC1251CMJ/883
T
MIN
s
T
A
s
T
MAX
b
40
§
C
s
T
A
s
a
85
C
b
55
§
C
s
T
A
s
a
125
§
C
b
55
§
C
s
T
A
s
a
125
§
C
DV
CC
and AV
CC
Voltage
(Notes 6 & 7)
Negative Supply Voltage (V
b
)
4.5V to 5.5V
b
4.5V to
b
5.5V
Reference Voltage
(V
REF
, Notes 6 & 7)
3.5V to AV
CC
a
50 mV
Converter Electrical Characteristics
The following specifications apply for V
CC
e
DV
CC
e
AV
CC
e a
5.0V, V
b
e b
5.0V, V
REF
e a
5.0V, AZ
e
‘‘1’’, f
CLK
e
3.5 MHz and tested using WR control unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other
limits T
A
e
T
J
e
25
§
C. (Notes 6, 7 and 8)
Symbol
Parameter
Conditions
Typical
(Note 9) (Notes 10, 19)
Limit
Units
(Limit)
STATIC CHARACTERISTICS
Positive Integral
Linearity Error
ADC1251BIJ
After Auto-Cal
(Notes 11 & 12)
g
0.6
LSB(max)
ADC1251CIJ
g
1
LSB(max)
ADC1251CMJ
g
1
LSB(max)
Negative Integral
Linearity Error
ADC1251BIJ
After Auto-Cal
(Notes 11 and 12)
g
0.6
LSB(max)
ADC1251CIJ
g
1
LSB(max)
ADC1251CMJ
g
1
LSB(max)
Missing Codes
After Auto-Cal (Notes 11 and 12)
0
Zero Error (Notes 12 and 13)
AZ
e
‘‘0’’ and f
CLK
e
1.75 MHz
g
2
LSB(max)
After Auto-Cal Only
g
2.0/
g
3.0
LSB(max)
Positive Full-Scale Error (Note 12)
AZ
e
‘‘0’’ and f
CLK
e
1.75 MHz
g
1.5
LSB(max)
After Auto-Cal Only
g
1.5/
g
2.0
LSB(max)
Negative Full-Scale Error (Note 12)
AZ
e
‘‘0’’ and f
CLK
e
1.75 MHz
g
1.5
LSB(max)
After Auto-Cal Only
g
1.5/
g
2.0
LSB(max)
C
REF
V
REF
Input Capacitance (Note 18)
80
pF
C
IN
Analog Input Capacitance
65
pF
V
IN
Analog Input Voltage
V
b
b
0.05
V
CC
a
0.05
V(min)
V(max)
Power Supply Sensitivity
Zero Error (Note 14) AV
CC
e
DV
CC
e
5V
g
5%,
Full-Scale ErrorV
REF
e
4.75V, V
b
e b
5V
g
5%
g
(/8
LSB
g
(/8
LSB
Linearity Error
g
(/8
LSB
2
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