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參數(shù)資料
| 型號(hào)： | ADC12662 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 12位，1.5兆赫，200毫瓦的A / D輸入多路復(fù)用器和轉(zhuǎn)換器采樣/保持 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 495K |
| 代理商： | ADC12662 |
Applications Information
(Continued)
2.0 THE ANALOG INPUT
The analog input of the ADC12662 can be modeled as two
small resistances in series with the capacitance of the input
hold capacitor (C
), as shown in Figure 7 The S/H switch is
closed during the Sample period, and open during Hold. The
source has to charge C
to the input voltage within the
sample period. Note that the source impedance of the input
voltage (R
SOURCE
) has a direct effect on the time it takes to
charge C
is too large, the voltage across C
IN
will not settle to within 0.5 LSBs of V
before the
conversion begins, and the conversion results will be incor-
rect. From a dynamic performance viewpoint, the combina-
tion of R
, R
MUX
, R
SW
, and C
IN
form a low pass filter.
Minimizing R
the input stage of the converter.
Typical values for the components shown in Figure 7 are:
R
= 100
, R
SW
= 100
, and C
IN
= 25 pF. The settling
time to n bits is:
t
SETTLE
= (R
SOURCE
+ R
MUX
+ R
SW
)
*
C
IN
*
n
*
ln (2).
The bandwidth of the input circuit is:
f
3dB
= 1/(2
*
3.14
*
(R
SOURCE
+ R
MUX
+ R
SW
)
*
C
IN
)
The ADC12662 is operated in a pipelined sequence, with
one hold capacitor acquiring the next sample while a con-
version is being performed on the voltage stored on the other
hold capacitor. This gives the source over t
seconds to
charge the hold capacitor to its final value. At 1.5 MHz, the
settling time must be less than 667 ns. Using the settling
time equation and component values given, the maximum
source impedance that will allow the input to settle to
1
2
LSB
(n = 13) at full speed is
～
2.8 k
. To ensure
1
2
LSB settling
over temperature and device-to-device variation, R
should be a maximum of 500
when the converter is oper-
ated at full speed.
If the signal source has a high output impedance, its output
should be buffered with an operational amplifier capable of
driving a switched 25 pF/100
load. Any ringing or instabili-
ties at the op amp’s output during the sampling period can
result in conversion errors. The LM6361 high speed op amp
is a good choice for this application due to its speed and its
ability to drive large capacitive loads. Figure 8 shows the
01187617
FIGURE 5. The Capacitive Voltage Divider
01187618
FIGURE 6. ADC Control Logic
A
www.national.com
14
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