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參數(shù)資料
| 型號： | ADC12662CIV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 12-Bit, 1.5 MHz, 200 mW A/D Converter with Input Multiplexer and Sample/Hold |
| 中文描述： | 2-CH 12-BIT FLASH METHOD ADC, PARALLEL ACCESS, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 495K |
| 代理商： | ADC12662CIV |
AC Electrical Characteristics
(Continued)
The following specifications apply for DV
= AV
= +5V, V
REF+(SENSE)
= +4.096V, V
= AGND, and f
s
= 1.5 MHz,
unless otherwise specified.
Boldface limits apply for T
A
= T
J
MIN
to T
MAX
;
all other limits T
A
= T
J
= +25C.
Symbol
Parameter
Conditions
Typ
Limit
(Note 8)
Units
(Limits)
(Note 7)
t
ACC
Access Time
(RD Low or OE High to Data Valid)
TRI-STATE Control
(RD High or OE Low to Databus TRI-STATE)
Delay from RD Low to INT High
C
L
= 100 pF
10
20
ns (max)
t
1H
, t
0H
R
L
= 1k, C
L
= 10 pF
25
40
ns (max)
t
INTH
C
L
= 100 pF
35
60
35
5
15
ns (max)
ns (min)
ns (max)
ns (max)
t
INTL
Delay from EOC High to INT Low
C
L
= 100 pF
25
t
UPDATE
EOC High to New Data Valid
Multiplexer Address Setup Time
(MUX Address Valid to EOC Low)
Multiplexer Address Hold Time
(EOC Low to MUX Address Invalid)
CS Setup Time
(CS Low to RD Low, S/H Low, or OE High)
CS Hold Time
(CS High after RD High, S/H High, or OE Low)
Wake-Up Time
(PD High to First S/H Low)
5
t
MS
50
ns (min)
t
MH
50
ns (min)
t
CSS
20
ns (min)
t
CSH
20
ns (min)
t
WU
1
μs
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the
listed test conditions.
Note 2:
All voltages are measured with respect to GND (GND = AGND = DGND), unless otherwise specified.
Note 3:
When the input voltage (V
IN
) at any pin exceeds the power supply rails (V
IN
<
GND or V
IN
>
V
CC
) the absolute value of current at that pin should be limited
to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX
,
θ
JA
and the ambient temperature T
A
. The maximum
allowable power dissipation at any temperature is P
D
= (T
JMAX
T
A
)/
θ
JA
or the number given in the Absolute Maximum Ratings, whichever is lower.
θ
JA
for the V
(PLCC) package is 55C/W.
θ
JA
for the VF (PQFP) package is 62C/W. In most cases the maximum derated power dissipation will be reached only during fault
conditions.
Note 5:
Human body model, 100 pF discharged through a 1.5 k
resistor. Machine model ESD rating is 200V.
Note 6:
See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in a current National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7:
Typicals are at +25C and represent most likely parametric norm.
Note 8:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 9:
Integral Linearity Error is the maximum deviation from a straight line between the measured offset and full scale endpoints.
Note 10:
Dynamic testing of the ADC12662 is done using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. See the graph in
the Typical Performance Characteristics section for a typical graph of THD performance vs input frequency with and without the input multiplexer.
Note 11:
The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation.
Note 12:
The contributions from the first nine harmonics are used in the calculation of the THD.
Note 13:
Effective Number of Bits (ENOB) is calculated from the measured signal-to-noise plus distortion ratio (SINAD) using the equation ENOB = (SINAD
1.76)/6.02.
Note 14:
The digital power supply current takes up to 10 seconds to decay to its final value after PD is pulled low. This prohibits production testing of the standby
current. Some parts may exhibit significantly higher standby currents than the 50 μA typical.
Note 15:
Power Supply Sensitivity is defined as the change in the Offset Error or the Full Scale Error due to a change in the supply voltage.
A
www.national.com
6
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