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參數(shù)資料
| 型號： | ADC14071CIVBH |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 14-Bit, 7 MSPS, 380 mW A/D Converter |
| 中文描述： | 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 427K |
| 代理商： | ADC14071CIVBH |
Specification Definitions
(Continued)
Distortion or SINAD. ENOB is defined as (SINAD -
1.76)/6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH
is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input. The test
is performed with f
equal to 100 kHz plus integer multiples
of f
. The input frequency at which the output is 3 dB
relative to the low frequency input signal is the full power
bandwidth.
INTERMODULATION DISTORTION (IMD)
is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to theADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dB.
INTEGRAL NON-LINEARITY (INL)
is a measure of the de-
viation of each individual code from a line drawn from nega-
tive full scale (
1
2
LSB below the first code transition) through
positive full scale (the last code transition). The deviation of
any given code from this straight line is measured from the
center of that code value.
NEGATIVE FULL SCALE ERROR
is the measure of how far
the last code transition is from the ideal of
1
2
LSB above
nominal negative full scale. It is the difference between the
input voltage (V
+
V
) just causing a transition to the first
code and the ideal voltage to cause that transition. The ideal
LSB transition (when it should occur) is (V
IN
+
) (V
IN
) =
1
2
LSB
OFFSET ERROR
is the difference between the ideal and ac-
tual voltages that cause a transition to mid-scale (a code of
8192) when approached from a lower code. The ideal LSB
transition (when it should occur) is (V
IN
+
) (V
IN
) = 0
Timing Diagram
PIPELINE DELAY (LATENCY)
is the number of clock cycles
between initiation of conversion and the availability of that
same conversion result at the output. New data is available
at every clock cycle, but the data lags the conversion by the
pipeline delay.
POSITIVE FULL SCALE ERROR
is a measure of how far
the last code transition is from the ideal of 1
1
2
LSB below
nominal positive full scale. It is the difference beween the in-
put voltage (V
IN
+
V
IN
) just causing a transition to positive
full scale and V
1
1
2
LSB. Full Scalse Error is sometimes
called Full Scale Offset Error.
SIGNAL TO NOISE RATIO (SNR)
is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the
sampling frequency, not including harmonics or dc.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD)
is the ratio, expressed in dB, of the rms value of the input sig-
nal to the rms value of all of the other spectral components
below half the clock frequency, including harmonics but ex-
cluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not
present at the input.
TOTAL HARMONIC DISTORTION (THD)
is the ratio, ex-
pressed in dB or dBc, of the rms total of the first nine har-
monic components to the rms value of the input signal.
DS101101-23
Output Timing
A
www.national.com
11
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