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參數(shù)資料
| 型號： | ADC16071 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters |
| 中文描述： | 16位Δ-Σ192 kS / s的模擬到數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | ADC16071 |
Pin Description
(Continued)
FSO
This is the Frame Sync Output pin.
FSO
is used
to
synchronize
an
external
ADC16071/ADC16471’s 32 SCO cycle data
transmission frame. The format of the signal on
FSO
depends on the logic level applied to the
SFMT
pin. See the
Serial Interface
section for
details.
device
to
the
TSI
This is the Time Slot Input pin.
TSI
can be used
to allow two ADC16071/ADC16471’s to share a
single serial data line. The logic level applied to
TSI
controls the active state of the ADC16071/
ADC16471’s
DOE
pin. See the
Serial Interface
and the
Two Channel Multiplexed Operation
sections for details.
DOE
This is the Data Output Enable pin.
DOE
is used
to control
SDO
’s TRI-STATE output buffer. The
active state of
DOE
is controlled by the logic lev-
el applied to the
TSI
pin. See the
Serial Inter-
face
and the
Two Channel Multiplexed Opera-
tion
sections for details.
Applications Information
TYPICAL PERFORMANCE RESULTS
Figure 6 shows a 16k point FFT plot of the baseband output
spectrum during conversion of a 24 kHz input signal.
CLOCK GENERATION
The ADC16071/ADC16471 requires a sampling-clock sig-
nal that is free of ringing (over/undershoot of no more than
100 mV
p-p
) and has a rise and fall time in the range of 3 ns–
10 ns. We have tested and recommended crystal clock os-
cillators from Ecliptek (EC1100 series) and SaRonix
(NCH060 and NCH080 series). Both of these families use
HCMOS logic circuitry for very fast rise and fall times.
TL/H/11454–13
FIGURE 6. Typical Performance of the ADC16071/ADC16471 at f
S
e
192 kHz, f
IN
e
24 kHz
13
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| ADC1610S080F1/DB,598 | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADC DEMO BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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