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參數資料
| 型號： | ADC16071 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters |
| 中文描述： | 16位Δ-Σ192 kS / s的模擬到數字轉換器 |
| 文件頁數： | 15/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | ADC16071 |
Applications Information
(Continued)
TL/H/11454–14
FIGURE 8. Two Channel Multiplexed Operation Connection Diagram
Best converter performance is achieved when these inter-
nal bypass capacitors are supplemented with additional ex-
ternal power-supply decoupling capacitors. This ensures the
lowest ac-bypass impedance path for the ADC16071/
ADC16471’s dynamic current requirements. Each of the
ADC16071/ADC16471’s four supply pins should be individ-
ually bypassed, using a parallel combination of 10
m
F (tan-
talum) and 0.1
m
F (monolithic ceramic), to its corresponding
ground pin:
V
A
a
(Pin 21)
x
AGND (Pin 4)
V
M
a
(Pin 20)
x
MGND (Pin 5)
V
D
a
(Pin 19)
x
DGND (Pin 6)
V
D
a
(Pin 18)
x
DGND (Pin 7)
Short lead lengths are mandatory. Therefore, surface mount
capacitors are
strongly
recommended.
POWER SUPPLY VOLTAGES FOR BEST
PERFORMANCE
While adequate performance will be achieved by operating
the ADC16071/ADC16471 with
a
5V connected to V
A
a
,
V
M
a
and V
D
a
, dynamic performance, as measured by
S/(N
a
D), can be further enhanced by slightly raising the
analog supply voltage and lowering the digital supply volt-
age.
ANALOG INPUT
The ADC16071 and the ADC16471 generate a two’s com-
plement output determined by the following equation:
Output Code
e
(V
IN
a b
V
IN
b
) (32768)
(V
REF
a b
V
REF
b
)
Round off to the nearest integer value between
b
32768
and 32767.
The signals applied to V
IN
a
and V
IN
b
must be between
V
A
a
and analog ground. For accurate conversions, the ab-
solute difference between V
IN
a
and V
IN
b
should be less
than the difference between V
REF
a
and V
REF
b
. Best har-
monic performance will result when a differential voltage is
applied to V
IN
a
and V
IN
b
that has a common mode voltage
at or below V
MID
.
Due to overloading in the ADC16071/ADC16471’s
DR
mod-
ulator, performance degrades considerably as the input am-
plitude approaches full scale. With an input that peaks at
b
2 dB from full scale, S/(N
a
D) is about 2 dB worse than
with a
b
6 dB input. With a
b
1 dB input, S/(N
a
D) can be
10 dB worse than with a
b
6 dB input.
15
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