參數(shù)資料
型號： ADC16071CIN
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： ADC
英文描述： 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters
中文描述： 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24
封裝： 0.300 INCH, PLASTIC, DIP-24
文件頁數(shù)： 14/20頁
文件大?。?/td> 355K
代理商： ADC16071CIN
Applications Information
(Continued)
Overshoot and ringing can be reduced by adding a series
damping resistor between the crystal oscillator’s output (pin
8) and the ADC16071/ADC16471’s CLK (pin 12), as shown
in Figure 7. The actual resistor value is dependent on the
board layout and trace length that connects the oscillator or
CLK source to the ADC. A typical starting value is 50
X
with
a range of 27
X
to 150
X
.
TL/H/11454–23
FIGURE 7. Damping Resistor Reduces
Clock Signal Overshoot
SERIAL INTERFACE
The ADC16071 and the ADC16471 have three serial inter-
face output pins: Serial Data Output
(SDO)
, Frame Sync
Output
(FSO)
, and Serial Clock Output
(SCO)
.
SCO
has a
frequency of f
CLK
/4. Each of the ADC16071/ADC16471’s
16-bit conversions is transmitted within the first half of the
data transmission frame
. A data transmission frame is 32
SCO cycles in duration. Two’s complement data shifts out
on the
SDO
pin beginning with bit 15 (MSB) and ending with
bit 0 (LSB), taking 16
SCO
cycles.
SDO
then shifts out
zeroes for the next 16
SCO
cycles to maintain compatibility
with two channel multiplexed operation.
The serial data that is shifted out of the
SDO
pin is synchro-
nous with
SCO
. Depending on the logic level applied to the
Serial Format pin
(SFMT)
, the data on the
SDO
pin is valid
on either the falling or rising edge of
SCO
. If a logic Low is
applied to
SFMT
, then the data on
SDO
is valid on the fall-
ing edge of
SCO
. If a logic High is applied to
SFMT
, then
the data on
SDO
is valid on the rising edge of
SCO
. See
Figure 2.
The
FSO
signal is used to synchronize other devices to the
ADC16071/ADC16471’s data transmission frame. Depend-
ing on the logic level applied to
SFMT
, the signal on
FSO
is
either a short pulse (approximately one SCO cycle in dura-
tion) ending just before the transmission of bit 15 on
SDO
,
or a square wave with a period of 32 SCO cycles going low
just before the transmission of bit 15 and going high just
after the transmission of bit 0. If a logic Low is applied to
SFMT
,
FSO
will be high for approximately one SCO cycle
and fall low just before the transmission of bit 15 and stay
low for the remainder of the transmission frame. If a logic
High is applied to
SFMT
,
FSO
will be low during the trans-
mission of bits 15–0 and high during the next 16 SCO cy-
cles. See Figure 3.
The Frame Sync Input (
FSI
), is used to synchronize the
ADC16071/ADC16471’s conversions to an external source.
The logic state of
FSI
is captured by the ADC16071/
ADC16471 on the falling edge of
CLK
. If an
FSI
low to high
transition is sensed between adjacent
CLK
falling edges,
the ADC16071/ADC16471 will interrupt its current data
transmission frame and begin a new one. See Figure 4.
Due to the data latency of the ADC16071/ADC16471’s digi-
tal filters, the first 31 conversions following a frame sync
input signal will represent inaccurate data, unless the frame
syncs are applied at constant 32 SCO cycle intervals. If no
FSI
signal is applied (FSI is kept High or Low), the
ADC16071/ADC16471 will internally create a frame sync
every 32 SCO cycles.
The Data Output Enable pin (
DOE
), is used to enable and
disable the output of data on
SDO
. When
DOE
is deactivat-
ed,
SDO
stops driving the serial data line by entering a high
impedance TRI-STATE.
DOE
’s active state matches the
logic level applied to the Time Slot Input pin (
TSI
). If a logic
Low is applied to
TSI
, the ADC16071/ADC16471’s
SDO
pin
will shift out data when
DOE
is Low, and be in a high imped-
ance TRI-STATE when
DOE
is High. If a logic High is ap-
plied to
TSI
,
SDO
will shift out data when
DOE
is High, and
be in a high impedance TRI-STATE when
DOE
is Low.
TWO CHANNEL MULTIPLEXED OPERATION
Two ADC16071/ADC16471’s can easily be configured to
share a single serial data line and operate in a ‘‘stereo’’, or
two channel multiplexed mode. They share the serial data
bus by alternating transmission of conversion data on their
respective
SDO
pins. One of the ADC16071/ADC16471’s,
the Master, shifts its conversion data out of
SDO
during the
first 16 SCO cycles of the data transmission frame. The
other ADC16071/ADC16471, the Slave, shifts its data out
during the second 16 SCO cycles of the data transmission
frame.
The Slave is selected by applying a logic High to its
TSI
pin
and a logic High to its
SFMT
pin. The Master is chosen by
applying a logic Low to its
TSI
pin and a logic High to its
SFMT
pin. As shown in Figure 8, the Master’s
FSO
is used
to control the
DOE
of both the Master and the Slave as well
as to synchronize the two ADC16071/ADC16471’s by driv-
ing the Slave’s Frame Sync Input pin,
FSI
. As the Master
finishes transmitting its 16 bits of conversion data, its
FSO
goes High. This triggers the Slave’s
FSI
, causing the Slave
to begin transmitting its 16 bits of conversion data.
The Master’s
DOE
is active Low and the Slave’s
DOE
is
active High. Since the same signal, the Master’s
FSO
, is
connected to both of the converters’
DOE
pins, one con-
verter will shift out data on its
SDO
pin while the other is in
TRI-STATE, allowing the two ADC16071/ADC16471’s to
share the same serial data transmission line.
POWER SUPPLY AND GROUNDING
The ADC16071/ADC16471 has on-chip 50 pF bypass ca-
pacitors between the supply-pin bonding pads and their cor-
responding grounds. There are 24 of these capacitors, 6 for
the analog section and 18 for the digital, resulting in a total
value of 1200 pF. They help control ringing on the on-chip
power supply busses, especially in the digital section. Fur-
ther, they help enhance the baseband noise performance of
the analog modulator.
14
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