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參數(shù)資料
| 型號： | ADC16071CIN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 16-Bit Delta-Sigma 192 ks/s Analog-to-Digital Converters |
| 中文描述： | 1-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-24 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 355K |
| 代理商： | ADC16071CIN |
DC Electrical Characteristics
The following specifications apply for V
A
a
e
V
D
a
e
V
M
a
e
5V unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e
25
§
C.
Symbol
Parameter
Conditions
Typical
(Note 6)
Limits
(Note 7)
Units
(Limit)
V
IH
Logic High Input Voltage
V
D
a
e
5.25V
V
D
a
2.3
V (max)
V (min)
V
IL
Logic Low Input Voltage
V
D
a
e
4.75V
0.8
b
0.3
V (max)
V (min)
V
OH
Logic High Output Current
e b
400
m
A,
V
D
a
e
4.75V
2.4
V (min)
V
OL
Logic Low Output Voltage
Logic Low Output Current
e
2 mA,
V
D
a
e
5.25V
0.5
V (max)
I
IN(1)
Logical ‘‘1’’ Input Current
1.0
5.0
m
A (max)
I
IN(0)
Logical ‘‘0’’ Input Current
b
1.0
b
5.0
m
A (max)
I
TSI
SDO TRI-STATE
é
Leakage Current
V
IN
e
0.4V to 2.4V
V
IN
e
0 to V
D
a
1.0
5.0
m
A (max)
C
IN
Logic Input Capacitance
5
pF
AC Electrical Characteristics for Clock In (CLK), Serial Clock Out (SCO), and
Frame Sync In (FSI)
The following specifications apply for V
A
a
e
V
D
a
e
V
M
a
e
5V unless otherwise specified.
Boldface limits apply for T
A
e
T
J
e
T
MIN
to T
MAX
; all other limits T
A
e
T
J
e
25
§
C.
Symbol
Parameter
Conditions
Typical
(Note 6)
Limits
(Note 7)
Units
(Limit)
f
CLK
CLK Frequency Range
(f
CLK
e
1/t
CLK
)
25
1
MHz (max)
MHz (min)
t
CLK
CLK Period
(t
CLK
e
1/f
CLK
)
1000
40
ns (max)
ns (min)
t
CLKL
CLK Low Pulse Width
16
ns (min)
t
CLKH
CLK High Pulse Width
14
ns (min)
t
R
CLK Rise Time
10
3
ns (max)
ns (min)
t
F
CLK Fall Time
10
3
ns (max)
ns (min)
t
FSILOW
Minimum Frame Sync Input
Low Time before Frame Sync
Input Asserted High
2
t
CLK
(min)
t
FSISU
Frame Sync Input Setup Time
10
ns (min)
t
FSIH
Frame Sync Input Hold Time
10
ns (min)
t
SCOD
Serial Clock Output Delay
Time from Rising Edge
of CLK
20
5
ns (max)
ns (min)
12
t
SCO
Serial Clock Output Period
4
t
CLK
5
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