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ADC76
2
SPECIFICATIONS
ELECTRICAL
At +25
°
C, and rated power supplies, unless otherwise noted.
ADC76J, K
ADC76A, B
MODEL
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
ANALOG INPUTS
Voltage Ranges: Bipolar
16
*
Bits
±
2.5,
±
5,
±
10
0 to +5, 0 to +10
0 to +20
*
*
*
V
V
Unipolar
Impedance (Direct Input)
0 to +5V,
±
2.5V
0 to +10V,
±
5.0V
0 to +20V,
±
10V
DIGITAL INPUTS
(1)
Convert Command
Logic Loading
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
(2)
Offset Error: Unipolar
(2)
Bipolar
(2)
Linearity Error: K, B
J, A
Inherent Quantization Error
Differential Linearity Error
Noise (3
σ
, p-p)
POWER SUPPLY SENSITIVITY
±
15VDC
+5VDC
CONVERSION TIME
(4)
14 Bits
15 Bits
16 Bits
WARM-UP TIME
DRIFT
Gain
Offset: Unipolar
Bipolar
Linearity
No Missing Codes Temp Range
J, A (13-bit)
K, B (14-bit)
OUTPUT DIGITAL DATA
(All codes complementary)
Parallel
Output Codes
(5)
: Unipolar
2.5
5
10
*
*
*
k
k
k
Positive pulse 50ns wide (min) trailing edge (“1” to “0” initiates conversion)
1
*
TTL Load
±
0.1
±
0.05
±
0.1
±
0.2
±
0.1
±
0.2
±
0.003
±
0.006
*
*
*
*
*
*
*
*
%
% of FSR
(3)
% of FSR
% of FSR
% of FSR
LSB
% of FSR
% of FSR
±
1/2
±
0.003
±
0.001
*
*
*
±
0.003
*
0.003
0.001
*
*
% of FSR/%V
S
% of FSR/%V
S
15
16
17
*
*
*
μ
s
μ
s
μ
s
Min
5
*
±
15
±
4
±
10
±
3
*
*
*
*
ppm/
°
C
±
2
*
ppm of FSR/
°
C
ppm of FSR/
°
C
ppm of FSR/
°
C
±
2
*
0
0
+70
+70
–25
–25
+85
+85
°
C
°
C
CSB
*
*
Bipolar
COB, CTC
(6)
Output Drive
Serial Data Code (NRZ)
Output Drive
Status
Status Output Drive
Internal Clock: Clock Output Drive
Frequency
(7)
POWER SUPPLY REOUIREMENTS
Power Consumption
Rated Voltage:Analog
Digital
Supply Drain: +15VDC
–15VDC
+5VDC
TEMPERATURE RANGE
Specification
Storage
2
*
TTL Loads
CSB, COB
*
2
*
TTL Loads
Logic “1” during conversion
*
2
2
*
*
*
TTL Loads
TTL Loads
kHz
933
1400
*
0.655
±
15
+5
+10
–28
+17
*
*
*
*
*
*
W
±
11.4
+4.75
±
16
+5.25
+15
–35
+20
*
*
*
*
*
*
*
VDC
VDC
mA
mA
mA
0
+70
+125
–25
*
+85
*
°
C
°
C
–55
*Specification same as ADC76J, K.
NOTES: (1) CMOS/TTL compatible, i.e., Logic “0” = 0.8V, max, Logic “1” = 2.0V, min for inputs. For digital outputs Logic “0” = 0.4V, max, Logic “1’ = 2.4V, min.
(2) Adjustable to zero. See “Optional External Gain and Offset Adjustment” section. (3) FSR means Full Scale Range. For example, unit connected for
±
10V range
has 20V FSR. (4) Conversion time may be shortened with “Short Cycle” set for lower resolution and with use of Clock Rate Control. See “Optional Conversion Time
Adjustment” section. The Clock Rate Control (pin 23) should be connected to Digital Common for specified conversion time. Short Cycle (pin 32) should be left open
for 16-bit resolution or connected to the n + 1 digital output for n-bit resolution. For example, connect Short Cycle to Bit 15 (pin 15) for 14-bit resolution. For resolutions
less than 16 bits, pin 32 should also be tied to +5V through a 2k
resistor. (5) See Table I. CSB = Complementary Straight Binary, COB = Complementary Offset
Binary, CTC = Complementary Two’s Complement. (6) CTC coding obtained by inverting MSB (pin 1). (7) Adjustable with Clock Rate Control from approximately
933kHz to 1.4MHz.