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參數(shù)資料
| 型號(hào)： | ADC76B |
| 英文描述： | 16-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | ADC76B |
ADC76
7
LAYOUT AND
OPERATING INSTRUCTIONS
LAYOUT PRECAUTIONS
Analog and digital common are not connected internally in
the ADC76, but should be connected together as close to the
unit as possible, preferably to a large plane under the ADC.
If these grounds must be run separately, use a wide conduc-
tor pattern and a 0.01
μ
F to 0.1
μ
F nonpolarized bypass
capacitor between analog and digital commons at the unit.
Low impedance analog and digital common returns are
essential for low noise performance. Coupling between
analog inputs and digital lines should be minimized by
careful layout. The comparator input (pin 27) is extremely
sensitive to noise. Any connection to this point should be as
short as possible and shielded by Analog Common or
±
15VDC supply patterns.
POWER SUPPLY DECOUPLING
The power supplies should be bypassed with tantalum or
electrolytic capacitors as shown in Figure 7 to obtain noise
free operation. These capacitors should be located close to
the ADC.
CONNECT
INPUT
SIGNAL
TO PIN
INPUT
SIGNAL
RANGE
CONNECT
PIN 26
TO PIN
CONNECT
PIN 24
TO
OUTPUT
CODE
±
10V
±
5V
±
2.5V
0 to +5V
0 to +10V
0 to +20V
COB or CTC*
COB or CTC*
COB or CTC*
CSB
CSB
CSB
27
27
27
22
22
22
Input Signal
Open
Pin 27
Pin 27
Open
Input Signal
24
25
25
25
25
24
*Obtained by inverting MSB pin 1.
TABLE II. ADC76 Input Scaling Connections.
OUTPUT DRIVE
Normally all ADC76 logic outputs will drive two standard
TTL loads; however, if long digital lines must be driven,
external logic buffers are recommended.
INPUT IMPEDANCE
The input signal to the ADC76 should be low impedance,
such as the output of an op amp, to avoid any errors due to
the relatively low input impedance of the ADC76.
If this impedance is not low, a buffer amplifier should be
added between the input signal and the direct input to the
ADC76 as shown in Figure 9.
INPUT SCALING
The analog input should be scaled as close to the maximum
input signal range as possible in order to utilize the maxi-
mum signal resolution of the A/D converter. Connect the
input signal as shown in Table II. See Figure 8 for circuit
details.
FIGURE 8. ADC76 Input Scaling Circuit.
FIGURE 9. Source Impedance Buffering.
FIGURE 7. Recommended Power Supply Decoupling.
OPTIONAL EXTERNAL GAIN
AND OFFSET ADJUSTMENTS
Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to the
ADC as shown in Figures 10 and 11. Multiturn potentiome-
ters with 100ppm/
°
C or better TCRs are recommended for
minimum drift over temperature and time. These pots may
be any value from 10k
to 100k
. All resistors should be
20% carbon or better. Pin 29 (Gain Adjust) and pin 27
(Offset Adjust) may be left open if no external adjustment is
required; however, pin 29 should always be bypassed with
0.01
μ
F to Analog Common.
ADJUSTMENT PROCEDURE
Offset—Connect the Offset potentiometer (make sure R
1
is
as close to pin 27 as possible) as shown in Figure 10.
Sweep the input through the end point transition voltage that
should cause an output transition to all bits off (E
IN
Off),
Figure 1.
30
28
22
21
19
1μF
+5VDC
Analog
Common
–15VDC
Digital
Common
+15VDC
1μF
+
+
+
1μF
27
26
25
24
22
Comparator
to Logic
From D/A
Converter
Direct
Input
R
2
R
1
5k
5k
Comp
In
Bipolar
Offset
V
REF
6.3k
Connect to
Pin 24 or Pin 25
+
–
Analog
Input Signal
10M
To Star (Meeting Point) Ground
OPA633
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