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參數(shù)資料
| 型號： | ADCLK846BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER 1:6 1.2GHZ 24LFCSP |
| 設計資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標準包裝： | 1,500 |
| 類型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，HSTL，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 頻率 - 最大： | 1.2GHz |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
ADCLK846
Rev. B | Page 12 of 16
CLOCK OUTPUTS
Each driver consists of a differential LVDS output or two single-
ended CMOS outputs (always in phase). When the LVDS driver
is enabled, the corresponding CMOS driver is in tristate. When
the CMOS driver is enabled, the corresponding LVDS driver is
the equivalent output stage.
OUTx
3.5mA
VS
3.5mA
07
22
6-
024
Figure 21. LVDS Output Simplified Equivalent Circuit
OUTxA
VS
OUTxB
VS
072
26
-02
5
Figure 22. CMOS Equivalent Output Circuit
CONTROL AND FUNCTION PINS
Logic Select for CTRL_A
CTRL_A selects either CMOS (high) or LVDS (low) logic for
Output 1 and Output 0. This pin has an internal 200 kΩ pull-
down resistor.
Logic Select for CTRL_B
CTRL_B selects either CMOS (high) or LVDS (low) logic for
Output 5, Output 4, Output 3, and Output 2. This pin has an
internal 200 kΩ pull-down resistor.
Sleep Mode
SLEEP powers down the chip except for the band gap. The
input is active high, which puts the outputs into a high-Z state.
This pin has a 200 kΩ pull-down resistor. The control pins are
operational during sleep mode.
POWER SUPPLY
The ADCLK846 requires a 1.8 V ± 5% power supply for VS.
Best practice recommends bypassing the power supply on
the PCB with adequate capacitance (>10 μF) and bypassing
all power pins with adequate capacitance (0.1 μF) as close to
the part as possible. The layout of the ADCLK846 evaluation
board (ADCLK846/PCBZ) provides a good layout example.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK846 package is an
electrical connection, as well as a thermal enhancement. For
the device to function properly, the paddle must be properly
attached to ground (GND). The ADCLK846 dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK846. The PCB attachment must provide a good thermal
path to a larger heat dissipation area, such as the ground plane
on the PCB. This requires a grid of vias from the top layer down
to the ground plane. See Figure 23 for an example.
VIAS TO GND PLANE
07
22
6-
026
Figure 23. PCB Land Example for Attaching Exposed Paddle
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相關代理商/技術參數(shù) |
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|---|---|
| ADCLK854 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer |
| ADCLK854/PCBZ | 功能描述:BOARD EVALUATION FOR ADCLK845 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| ADCLK854BCPZ | 功能描述:IC CLOCK BUFFER MUX 2:12 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 產(chǎn)品培訓模塊:High Bandwidth Product Overview 標準包裝:1,000 系列:Precision Edge® 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:4 差分 - 輸入:輸出:是/是 輸入:CML，LVDS，LVPECL 輸出:CML 頻率 - 最大:2.5GHz 電源電壓:2.375 V ~ 2.625 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) |
| ADCLK854BCPZ-REEL7 | 功能描述:IC CLOCK BUFFER MUX 2:12 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘緩沖器，驅(qū)動器 系列:- 標準包裝:74 系列:- 類型:扇出緩沖器（分配） 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 輸入:HCSL, LVCMOS, LVDS, LVPECL, LVTTL 輸出:HCSL，LVDS 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:管件 |
| ADCLK905 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrafast SiGe ECL Clock/Data Buffers |
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