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參數(shù)資料
| 型號： | ADCLK950BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/12頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:10 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | SIGe |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 4.8GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
ADCLK950
Rev. A | Page 9 of 12
FUNCTIONAL DESCRIPTION
CLOCK INPUTS
The ADCLK950 accepts a differential clock input from one of
two inputs and distributes the selected clock to all 10 LVPECL
outputs. The maximum specified frequency is the point at which
the output voltage swing is 50% of the standard LVPECL swing
the General Description section for more clock input details.
termination schemes.
Output jitter performance is degraded by an input slew rate
below 4 V/ns, as shown in Figure 12. The ADCLK950 is
specifically designed to minimize added random jitter over a
wide input slew rate range. Whenever possible, clamp excessively
large input signals with fast Schottky diodes because attenuators
reduce the slew rate. Input signal runs of more than a few
centimeters should be over low loss dielectrics or cables with
good high frequency characteristics.
CLOCK OUTPUTS
The specified performance necessitates using proper transmission
line terminations. The LVPECL outputs of the ADCLK950 are
designed to directly drive 800 mV into a 50 Ω cable or into
microstrip/stripline transmission lines terminated with 50 Ω
output stage is shown in Figure 13. The outputs are designed for
best transmission line matching. If high speed signals must be
routed more than a centimeter, either the microstrip or the
stripline technique is required to ensure proper transition times
and to prevent excessive output ringing and pulse width depen-
dent propagation delay dispersion.
VEE
VCC
Qx
08
27
9-
0
13
Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage
termination schemes. When dc-coupled, VS of the receiving buffer
should match VS_DRV.
Thevenin-equivalent termination uses a resistor network to
provide 50 Ω termination to a dc voltage that is below VOL of
the LVPECL driver. In this case, VS_DRV on the ADCLK950
should equal VS of the receiving buffer. Although the resistor
combination shown (in Figure 15) results in a dc bias point of
VS_DRV 2 V, the actual common-mode voltage is VS_DRV
1.3 V because there is additional current flowing from the
ADCLK950 LVPECL driver through the pull-down resistor.
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue.
VS_DRV
Z0 = 50
VS = VS_DRV
LVPECL
50
VCC – 2V
50
Z0 = 50
ADCLK950
08
27
9-
0
1
4
Figure 14. DC-Coupled, 3.3 V LVPECL
VS_DRV
50
SINGLE-ENDED
(NOT COUPLED)
VS
VS_DRV
LVPECL
127
83
ADCLK950
0
82
79
-01
5
Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination
VS_DRV
Z0 = 50
VS = VS_DRV
LVPECL
50
Z0 = 50
ADCLK950
0
82
79-
0
16
Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination
VS_DRV
100 DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VS
LVPECL
100
0.1nF
200
ADCLK950
08
27
9-
01
7
Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line
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| ADCLK954/PCBZ | 功能描述:KIT EVAL CLK BUFF ADCLK954 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SIGe 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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