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參數(shù)資料
型號: ADCMP671-1YUJZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 10/16頁
文件大?。?/td> 0K
描述: IC MONITOR UV/OV LP ADJ 6TSOT
標準包裝: 1
類型: 通用
元件數(shù): 1
輸出類型: 開路漏極
電壓 - 電源,單路/雙路(±): 1.7 V ~ 5.5 V
電流 - 輸入偏壓(最小值): 2.5nA
電流 - 靜態(tài)(最大值): 11µA
傳輸延遲(最大): 10µs
磁滯: 9.2mV
工作溫度: -40°C ~ 125°C
封裝/外殼: SOT-23-6 細型,TSOT-23-6
安裝類型: 表面貼裝
包裝: 標準包裝
其它名稱: ADCMP671-1YUJZ-RL7DKR
Data Sheet
ADCMP671
Rev. 0 | Page 3 of 16
SPECIFICATIONS
VDD = 1.7 V to 5.5 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
THRESHOLDS1
Rising Input Threshold Voltage (VTH(R))
396.6
400.4
404.3
mV
VDD = 1.7 V
399.3
400.4
401.5
mV
VDD = 3.3 V
398.5
400.4
402.2
mV
VDD = 5.5 V
Falling Input Threshold Voltage(VTH(F))
387
391
395.4
mV
VDD = 1.7 V
389.2
391
392.9
mV
VDD = 3.3 V
388.5
391
393.2
mV
VDD = 5.5 V
Rising Input Threshold Voltage Accuracy
±0.275
%
VDD = 3.3 V
Falling Input Threshold Voltage Accuracy
±0.475
%
VDD = 3.3 V
Hysteresis = VTH(R) VTH(F)
7.8
9.2
11.1
mV
INPUT CHARACTERISTICS
Input Bias Current
0.01
1
nA
VDD = 1.7 V, VIN = VDD
0.01
1
nA
VDD = 1.7 V, VIN = 0.1 V
OPEN-DRAN OUTPUTS
Output Low Voltage2
140
200
mV
VDD = 1.7 V, IOUT = 3 mA
130
200
mV
VDD = 5.5 V, IOUT = 5 mA
Output Leakage Current3
0.01
0.1
μA
VDD = 1.7 V, VOUT = VDD
0.01
0.1
μA
VDD = 1.7 V, VOUT = 5.5 V
DYNAMIC PERFORMANCE2, 4
High-to-Low Propagation Delay
10
μs
VDD = 5.5 V, VOL = 400 mV
Low-to-High Propagation Delay
8
μs
VDD = 5.5 V, VOH = 0.9 × VDD
Output Rise Time
0.5
μs
VDD = 5.5 V, VOUT = (0.1 to 0.9) × VDD
Output Fall Time
0.07
μs
VDD = 5.5 V, VOUT = (0.1 to 0.9) × VDD
POWER SUPPLY
Supply Current5
5.7
10
μA
VDD = 1.7 V
6.5
11
μA
VDD = 5.5 V
1 RL = 100 kΩ, VOUT = 2 V swing.
2 VIN = 10 mV input overdrive.
3 VIN = 40 mV overdrive.
4 RL = 10 kΩ.
5 No load current.
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