參數(shù)資料
型號: ADCMP671-1YUJZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 6/16頁
文件大?。?/td> 0K
描述: IC MONITOR UV/OV LP ADJ 6TSOT
標準包裝: 1
類型: 通用
元件數(shù): 1
輸出類型: 開路漏極
電壓 - 電源,單路/雙路(±): 1.7 V ~ 5.5 V
電流 - 輸入偏壓(最小值): 2.5nA
電流 - 靜態(tài)(最大值): 11µA
傳輸延遲(最大): 10µs
磁滯: 9.2mV
工作溫度: -40°C ~ 125°C
封裝/外殼: SOT-23-6 細型,TSOT-23-6
安裝類型: 表面貼裝
包裝: 標準包裝
其它名稱: ADCMP671-1YUJZ-RL7DKR
ADCMP671
Data Sheet
Rev. 0 | Page 14 of 16
APPLICATIONS INFORMATION
The ADCMP671 is a UV and OV monitor with a built-in 400 mV
reference that operates from 1.7 V to 5.5 V. The comparator is
0.275% accurate with a built-in hysteresis of 9.2 mV. The outputs
are open-drain, capable of sinking 40 mA.
COMPARATORS AND INTERNAL REFERENCE
There are two comparators inside the ADCMP671. The
comparator with its noninverting input connected to the INH
pin (and its inverting input connected internally to the 400 mV
reference) is for undervoltage detection, and the comparator
with its inverting input available through the INL pin (and its
noninverting input connected internally to the 400 mV reference)
is for overvoltage detection. The rising input threshold voltage of
the comparators is designed to be equal to that of the reference.
POWER SUPPLY
The ADCMP671 is designed to operate from 1.7 V to 5.5 V.
A 0.1 μF decoupling capacitor is recommended between VDD
and GND.
INPUTS
The comparator inputs are limited to the maximum VDD voltage
range. The voltage on these inputs can be more than VDD but never
more than the maximum allowed VDD voltage. When adding a
resistor string to the input, choose resistor values carefully because
the input bias current is in parallel with the bottom resistor of
the string. Therefore, choose the bottom resistor first to control
the error introduced by the bias current.
To minimize the number of external components use three
resistor dividers to program the UV and OV thresholds.
HYSTERESIS
To prevent oscillations at the output caused by noise or slowly
moving signals passing the switching threshold, each comparator
has a built-in hysteresis of approximately 8.9 mV.
VOLTAGE MONITORING SCHEME
When monitoring a supply rail, the desired nominal operating
voltage for monitoring is denoted by VM, IM is the nominal current
through the resistor divider, VOV is the overvoltage trip point,
and VUV is the undervoltage trip point.
Figure 34 illustrates the voltage monitoring input connection.
Three external resistors, RX, RY, and RZ, divide the positive voltage
for monitoring (VM) into the high-side voltage (VH) and low-
side voltage (VL). The high-side voltage is connected to the INH
pin, and the low-side voltage is connected to the INL pin.
INH
UV
OV
INL
VDD
GND
12V
RX
RY
RZ
5V
400mV
ADCMP671
PWRGD
OV
101
60-
034
Figure 34. Undervoltage/Overvoltage Monitoring Configuration
To trigger an overvoltage condition, the low-side voltage (in this
case, VL) must exceed the 0.4 V threshold on the INL pin. The
low-side voltage, VL, is given by the following equation:
V
4
.
0
=
+
=
Z
Y
X
Z
OV
L
R
V
Also,
M
Z
Y
X
I
V
R
=
+
Therefore, RZ, which sets the desired trip point for the overvoltage
monitor, is calculated using the following equation:
( )
()()
M
OV
M
Z
I
V
R
)
4
.
0
(
=
To trigger the undervoltage condition, the high-side voltage, VH,
must fall below the 0.4 V threshold on the INH pin. The high-
side voltage, VH, is given by the following equation:
V
4
.
0
=
+
=
Z
Y
X
Z
Y
UV
H
R
V
Because RZ is already known, RY can be expressed as follows:
( )
()() Z
M
UV
M
Y
R
I
V
R
=
)
4
.
0
(
When RY and RZ are known, RX is calculated using the following
equation:
( )
()
Y
Z
M
X
R
I
V
R
=
If VM, IM, VOV, or VUV changes each step must be recalculated.
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