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參數(shù)資料
| 型號： | ADDI7100BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROCESSOR CCD SIGNAL7 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 類型： | CCD 信號處理器，12 位 |
| 應(yīng)用： | 數(shù)碼相機 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
ADDI7100
Rev. C | Page 8 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
24 REFB
23 REFT
22 CCDIN
21 AVSS
D2 1
D3 2
D4 3
32
D1
20 AVDD
19 SHD
18 SHP
17 CLPOB
D
10
9
D
11
10
DR
V
D
11
D
R
V
SS
1
2
DV
DD
13
D
A
TACL
K
14
D
VSS
15
PB
L
K
16
D5 4
D6 5
D7 6
D8 7
D9 8
31
D0
30
NC
29
NC
28
V
D
27
S
C
K
26
S
D
A
TA
25
S
L
NOTES
1. IT IS RECOMMENDED THAT THE EXPOSED
PAD BE SOLDERED TO THE GROUND PLANE
OF THE PCB.
2. NC = NO CONNECT.
07
60
8-
00
3
ADDI7100
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1 to 10
D2 to D11
DO
Digital Data Outputs.
11
DRVDD
P
Digital Output Driver Supply.
12
DRVSS
P
Digital Output Driver Ground.
13
DVDD
P
Digital Supply.
14
DATACLK
DI
Digital Data Output Latch Clock.
15
DVSS
P
Digital Supply Ground.
16
PBLK
DI
Preblanking Clock Input.
17
CLPOB
DI
Black Level Clamp Clock Input.
18
SHP
DI
CDS Sampling Clock for CCD Reference Level.
19
SHD
DI
CDS Sampling Clock for CCD Data Level.
20
AVDD
P
Analog Supply.
21
AVSS
P
Analog Ground.
22
CCDIN
AI
Analog Input for CCD Signal.
23
REFT
AO
ADC Top Reference Voltage Decoupling.
24
REFB
AO
ADC Bottom Reference Voltage Decoupling.
25
SL
DI
Serial Digital Interface Load Pulse.
26
SDATA
DI
Serial Digital Interface Data Input.
27
SCK
DI
Serial Digital Interface Clock Input.
28
VD
DI
Vertical Sync Input. Controls the update time of VD-updated registers. If this pin is not
needed, it should be tied to GND.
29, 30
NC
Not Internally Connected.
31, 32
D0, D1
DO
Digital Data Output.
1 AI = analog input, AO = analog output, DI = digital input, DO = digital output, P = power, and NC = no connect.
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