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參數(shù)資料
| 型號(hào)： | ADF4118BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL RF FREQ SYNTHESZR 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4118EBZ1-ND - BOARD EVAL FOR ADF4118 |
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ADF4116/ADF4117/ADF4118
Rev. D | Page 20 of 28
Fastlock Mode 2 uses the values in the timer counter to
determine the timeout period before reverting to normal
mode operation after fastlock. Fastlock Mode 2 is chosen
by setting DB11 to 1.
The user must also decide how long to keep the high
current (1 mA) active before reverting to low current
(250 μA). This is controlled by the timer counter control
bits, DB14 to DB11 (TC4 to TC1), in the function latch.
The truth table is given in Figure 33.
To program a new output frequency, program the A counter
and B counter latch with new values for A and B. At the
same time, set the CP Gain bit to a 1, which sets the charge
pump to 1 mA for a period of time determined by TC4 to
TC1. When this time is up, the charge pump current
reverts to 250 μA. At the same time, the CP Gain bit in the
A counter and B counter latch is reset to 0 and is ready for
the next time that the user wants to change the frequency.
INITIALIZATION LATCH
When C2 and C1 are both set to 1, the initialization latch is
programmed. This is essentially the same as the function latch
that is programmed when C2, C1 = 1, 0.
However, when the initialization latch is programmed, an
additional internal reset pulse is applied to the R counter and
N counter. This pulse ensures that the N counter is at a load
point when the N counter data is latched and that the device
begins counting in close phase alignment.
If the latch is programmed for synchronous power-down (CE
pin is high; PD1 bit is high; PD2 bit is low), the internal pulse
also triggers this power-down. The prescaler reference and the
oscillator input buffer are unaffected by the internal reset pulse,
so close phase alignment is maintained when counting resumes.
When the first N counter data is latched after initialization, the
internal reset pulse is again activated. However, successive
N counter loads do not trigger the internal reset pulse.
DEVICE PROGRAMMING AFTER
INITIAL POWER-UP
After initial power-up, the device can be programmed by the
initialization latch method, the CE pin method, or the counter
reset method.
Initialization Latch Method
1.
Apply VDD.
2.
Program the initialization latch (11 in 2 LSBs of input
word). Make sure that F1 bit is programmed to 0.
3.
Do an R load (00 in 2 LSBs).
4.
Do an N load (01 in 2 LSBs).
When the initialization latch is loaded, the following occurs:
The function latch contents are loaded.
An internal pulse resets the R, N, and timeout counters to
load state conditions and also three-states the charge pump.
Note that the prescaler band gap reference and the oscillator
input buffer are unaffected by the internal reset pulse, allowing
close phase alignment when counting resumes.
Latching the first N counter data after the initialization
word activates the same internal reset pulse. Successive
N loads do not trigger the internal reset pulse unless there
is another initialization.
CE Pin Method
1.
Apply VDD.
2.
Bring CE low to put the device into power-down. This is an
asynchronous power-down in that it happens immediately.
3.
Program the function latch (10).
4.
Program the R counter latch (00).
5.
Program the N counter latch (01).
6.
Bring CE high to take the device out of power-down.
The R counter and N counter resume counting in close alignment.
Note that after CE goes high, a duration of 1 μs may be required
for the prescaler band gap voltage and oscillator input buffer
bias to reach a steady state.
CE can be used to power up and power down the device to check
for channel activity. The input register does not need to be repro-
grammed each time the device is disabled and enabled, as long
as it is programmed at least once after VCC is initially applied.
Counter Reset Method
1.
Apply VDD.
2.
Do a function latch load (10 in 2 LSBs). As part of this,
load 1 to the F1 bit. This enables the counter reset.
3.
Do an R counter load (00 in 2 LSBs).
4.
Do an N counter load (01 in 2 LSBs).
5.
Do a function latch load (10 in 2 LSBs). As part of this,
load 0 to the F1 bit. This disables the counter reset.
This sequence provides the same close alignment as the initiali-
zation method. It offers direct control over the internal reset.
Note that counter reset holds the counters at load point and
three-states the charge pump, but it does not trigger synchro-
nous power-down. The counter reset method requires an extra
function latch load compared to the initialization latch method.
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADF4118BRUZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4118BRUZ-RL7 | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4118BRUZ-RL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4118YRUZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADF4118YRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
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