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參數(shù)資料
| 型號： | ADF4118BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL RF FREQ SYNTHESZR 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4118EBZ1-ND - BOARD EVAL FOR ADF4118 |
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ADF4116/ADF4117/ADF4118
Rev. D | Page 12 of 28
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 25. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
TO R COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
BUFFER
00
39
2-
02
5
Figure 25. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 26. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
AVDD
AGND
500
1.6V
BIAS
GENERATOR
RFINA
RFINB
00
39
2-
0
26
Figure 26. RF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler takes the CML clock
from the RF input stage and divides it down to a manageable
frequency for the CMOS A counter and CMOS B counter. The
prescaler is programmable. It can be set in software to 8/9 for the
ADF4116 and to 32/33 for the ADF4117 and ADF4118. It is based
on a synchronous 4/5 core.
A COUNTER AND B COUNTER
The A CMOS counter and B CMOS counter combine with the
dual-modulus prescaler to allow a wide ranging division ratio in
the PLL feedback counter. The counters are specified to work
when the prescaler output is 200 MHz or less.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is as follows:
(
)
[
]
R
f
A
B
P
f
REFIN
VCO
/
×
+
×
=
where:
fVCO is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler.
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 5-bit swallow counter (0 to 31).
fREFIN is the output frequency of the external reference frequency
oscillator.
R is the preset divide ratio of binary 14-bit programmable
reference counter (1 to 16,383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
13-BIT
B COUNTER
5-BIT
A COUNTER
PRESCALER
P/P + 1
FROM RF
INPUT STAGE
MODULUS
CONTROL
N = BP + A
LOAD
TO PFD
0
039
2-
0
27
Figure 27. A Counter and B Counter
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4118BRUZ-RL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4118BRUZ-RL7 | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| ADF4118BRUZ-RL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
| ADF4118YRUZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADF4118YRUZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
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