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參數(shù)資料
| 型號： | ADF4153YRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH FRACT-N FREQ 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 分?jǐn)?shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 4GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4153EBZ1-ND - BOARD EVAL FOR ADF4153 |
Data Sheet
ADF4153
Rev. F | Page 21 of 24
When operating in this mode, the maximum SCLOCK rate of
the ADuC812 is 4 MHz. This means that the maximum rate at
which the output frequency can be changed is 180 kHz.
ADSP-21xx Interface
Figure 19 shows the interface between the ADF4153 and the
ADSP-21xx digital signal processor. As discussed previously,
the ADF4153 needs a 24-bit serial word for each latch write.
The easiest way to accomplish this using the ADSP-21xx family
is to use the autobuffered transmit mode of operation with
alternate framing. This provides a means for transmitting an
entire block of serial data before an interrupt is generated.
Set up the word length for eight bits and use three memory
locations for each 24-bit word. To program each 24-bit latch,
store the three 8-bit bytes, enable the autobuffered mode, and
write to the transmit register of the DSP. This last operation
initiates the autobuffer transfer.
ADSP-21xx
ADF4153
SCLK
CLK
DATA
LE
MUXOUT
(LOCK DETECT)
DT
TFS
I/O FLAGS
03685-
025
Figure 19. ADSP-21xx to ADF4153 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board (PCB) pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the
pad. This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the PCB should be at least as large as this
exposed pad. On the PCB, there should be a clearance of at least
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
thermal performance of the package. If vias are used, they should
be incorporated in the thermal pad at 1.2 mm pitch grid. The
via diameter should be between 0.3 mm and 0.33 mm, and the
via barrel should be plated with one ounce of copper to plug the
via. The user should connect the PDB thermal pad to AGND.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4153YRUZ-RL7 | 功能描述:IC SYNTH FRACT-N FREQ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4154 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| ADF4154BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Bulk |
| ADF4154BCP-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Tape and Reel |
| ADF4154BCP-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R |
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