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參數(shù)資料
| 型號： | ADF4153YRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTH FRACT-N FREQ 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 分?jǐn)?shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 4GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4153EBZ1-ND - BOARD EVAL FOR ADF4153 |
Data Sheet
ADF4153
Rev. F | Page 5 of 24
Parameter
B Version1
Y Version2
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
220
dBc/Hz typ
PLL loop BW = 500 kHz
114
dBc/Hz typ
Measured at 10 kHz offset, normalized to 1 GHz
Phase Noise Performance7
@ VCO output
1750 MHz Output8
102
dBc/Hz typ
@ 5 kHz offset, 25 MHz PFD frequency
1
Operating temperature for B version is 40°C to +85°C.
2
Operating temperature for Y version is 40°C to +125°C.
3
AC coupling ensures AVDD/2 bias.
4
Guaranteed by design. Sample tested to ensure compliance.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider
value) and 10 log(FPFD). PNSYNTH = PNTOT 10 log(FPFD) 20 log(N).
6
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF,
and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
7
The phase noise is measured with the EV-ADF4153SD1Z and the Agilent E5500 phase noise system.
8
fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode.
TIMING SPECIFICATIONS
AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted;
dBm referred to 50 .
Table 2.
Parameter
Limit at TMIN to TMAX (B Version)
Unit
Test Conditions/Comments
t1
20
ns min
LE setup time
t2
10
ns min
DATA to CLK setup time
t3
10
ns min
DATA to CLK hold time
t4
25
ns min
CLK high duration
t5
25
ns min
CLK low duration
t6
10
ns min
CLK to LE setup time
t7
20
ns min
LE pulse width
CLK
DATA
LE
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t1
t2
t3
t7
t6
t4
t5
03685-
026
Figure 2. Timing Diagram
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| ADF4153YRUZ-RL7 | 功能描述:IC SYNTH FRACT-N FREQ 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4154 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fractional-N Frequency Synthesizer |
| ADF4154BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Bulk |
| ADF4154BCP-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R 制造商:Rochester Electronics LLC 功能描述:FRACTIONAL-N SYNTH. W/FASTLOCK COUNTER - Tape and Reel |
| ADF4154BCP-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 20-Pin LFCSP EP T/R |
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