參數(shù)資料
型號(hào)： ADF4193BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 7/32頁(yè)
文件大?。?/td> 0K
描述： IC PLL FREQ SYNTHESIZER 32LFCSP
標(biāo)準(zhǔn)包裝： 5,000
類(lèi)型： 時(shí)鐘/頻率合成器，RF
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 2:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 3.5GHz
除法器/乘法器： 是/是
電源電壓： 2.7 V ~ 3.3 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
配用： EVAL-ADF4193EBZ2-ND - BOARD EVALUATION EB2 FOR ADF4193
EVAL-ADF4193EBZ1-ND - BOARD EVALUATION EB1 FOR ADF4193
Data Sheet
ADF4193
Rev. F | Page 15 of 32
FRAC/INT REGISTER (R0)
05328-023
DB23
RESERVED
0
DB22
N8
DB21
N7
DB20
N6
DB19
N5
DB18
N4
DB17
N3
DB16
N2
DB15
N1
DB14
F12
DB13
F11
DB12
F10
DB11
F9
DB10
F8
DB9
F7
DB8
F6
DB7
F5
DB6
F4
DB5
F3
DB4
F2
DB3
F1
DB2
C3 (0)
DB1
C2 (0)
DB0
C1 (0)
8-BIT RF INT VALUE
12-BIT RF FRAC VALUE
CONTROL
BITS
F12
0
.
1
F11
0
.
1
F10
0
.
1
..........
F3
0
.
1
F2
0
1
.
0
1
F1
0
1
0
1
.
0
1
0
1
FRACTIONAL VALUE (FRAC)
0
1
2
3
.
4092
4093
4094
4095
N8
0
.
1
N7
0
.
1
N6
0
.
1
N5
1
.
1
N4
1
.
1
N3
0
.
1
N2
1
.
1
N1
0
.
1
INTEGER VALUE (INT)
26
.
255
0 = < FRAC < MOD
Figure 29. FRAC/INT Register (R0)
R0, the FRAC/INT register, is used to program the synthesizer
output frequency. On the next PFD cycle following a write to
R0, the N divider section is updated with the new INT and
FRAC values. At the same time, the PLL automatically enters
fast lock mode and the charge pump current is increased to its
maximum value and stays at this value until the ICP timeout
counter times out, and switches SW1, SW2, and SW3 closed
and remains closed until the SW1, SW2, and SW3 timeout
counters time out.
Once all registers are programmed during the initialization
sequence (see Table 8), all that is required thereafter to program
a new channel is a write to R0. However, as described in the
Programming section, it can also be desirable to program R1
and R2 register settings on a channel-by-channel basis. These
settings are double buffered by the write to R0. This means
that while the data is loaded through the serial interface on the
respective R1 and R2 write cycles, the synthesizer is not updated
with their data until the next write to Register R0.
Control Bits
The three LSBs, Control Bit C3, Control Bit C2, and Control Bit C1,
should be set to 0, 0, 0, respectively, to select R0, the FRAC/INT
register.
Reserved Bit
Bit DB23 is reserved and must be set to 0.
8-Bit INT Value
These eight bits set the INT value, which determines the integer
part of the feedback division factor. All integer values from 26
to 255 are allowed. See the Worked Example section.
12-Bit FRAC Value
The 12 FRAC bits set the numerator of the fraction that is input
to the Σ-Δ modulator. This, along with INT, specifies the new
frequency channel that the synthesizer locks to, as shown in the
Worked Example section. FRAC values from 0 to MOD 1
cover channels over a frequency range equal to the PFD reference
frequency.
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參數(shù)描述
ADF4193BCPZ-RL7 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
ADF4193SP1BCPZ 制造商:Analog Devices 功能描述:
ADF4193SP1BCPZ-RL7 制造商:Analog Devices 功能描述:
ADF4193SP2BCPZ-RL7 制造商:Analog Devices 功能描述:
ADF4193WCCPZ-RL7 功能描述:IC PLL FREQ SYNTHESIZER 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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