參數(shù)資料
型號(hào)： ADF4206
廠商： Analog Devices, Inc.
元件分類： XO, clock
英文描述： Dual RF PLL Frequency Synthesizers
中文描述： 雙射頻鎖相環(huán)頻率合成器
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 206K
代理商： ADF4206
REV. 0
ADF4206/ADF4207/ADF4208
–18–
APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver
Figure 7 shows the ADF4207 being used in a classic superhet-
erodyne receiver to provide the required LOs (Local Oscillators).
In this circuit, the reference input signal is applied to the circuit
at OSC
IN
and is being generated by a 10 MHz Crystal Oscillator.
This is a low-cost solution and for better performance over tem-
perature, a TCXO (Temperature Controlled Crystal Oscillator)
may be used instead.
In order to have a channel spacing of 200 kHz (the GSM stan-
dard), the reference input must be divided by 50, using the
on-chip reference counter.
The RF output frequency range is 1050 MHz to 1086 MHz. Loop
filter component values are chosen so that the loop bandwidth is
20 kHz. The synthesizer is set up for a charge pump current of
4.375 mA and the VCO sensitivity is 15.6 MHz/V.
OSC
OUT
MUXOUT
ADF4208
V
P
2
CP
RF2
V
DD
2 V
DD
1
V
P
1
CP
RF1
RF2
IN
RF1
IN
OSC
IN
CLK
DATA
LE
D
R
D
R
A
R
A
R
DECOUPLING CAPACITORS (22 F/10pF) ON V
, V
OF
THE ADF4208, AND ON V
OF THE VCOs HAVE BEEN
OMITTED FROM THE DIAGRAM TO AID CLARITY.
VCO190-200T
V
CC
V
CC
S
100pF
18
18
18
100pF
IF
OUT
100pF
51
30pF
10MHz
18k
1.3nF
13nF
2.7k
620pF
3.3k
V
P
V
DD
V
P
100pF
18
RF
OUT
100pF18
18
100pF
51
LOCK DETECT
30pF
VCO190-1750T
Figure 8. Local Oscillator for WCDMA Receiver Using the ADF4208
The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.
Local Oscillator for WCDMA Receiver
Figure 8 shows the ADF4208 being used to generate the local
oscillator frequencies for a Wideband CDMA (WCDMA) system.
The RF output range needed is 1720 MHz to 1780 MHz. The
VCO190–1750T will accomplish this. Channel spacing is
200 kHz with a 20 kHz loop bandwidth. VCO sensitivity is
32 MHz/V. Charge pump current of 4.375 mA is used and
the desired phase margin for the loop is 45
°
.
The IF output is fixed at 200 MHz. The VCO190–200T is used.
It has a sensitivity of 10 MHz/V. Channel spacing and loop
bandwidth is chosen to be the same as the RF side.
相關(guān)PDF資料
PDF描述
ADF4206BRU Dual RF PLL Frequency Synthesizers
ADF4212 Dual RF/IF PLL Frequency Synthesizers
ADF4210 Dual RF/IF PLL Frequency Synthesizers
ADF4210BCP Dual RF/IF PLL Frequency Synthesizers
ADF4210BRU Dual RF/IF PLL Frequency Synthesizers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADF4206BRU 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP
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ADF4206BRUZ-R7 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP T/R
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