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參數(shù)資料
| 型號： | ADF4206 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | 雙射頻鎖相環(huán)頻率合成器 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 206K |
| 代理商： | ADF4206 |
REV. 0
–3–
ADF4206/ADF4207/ADF4208
Parameter
B Version
B Chips
2
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Phase Noise Floor (RF1)
7
ADF4206
ADF4207
ADF4208
ADF4206
ADF4207
ADF4208
Phase Noise Performance
8
ADF4206 (RF1, RF2)
ADF4207 (RF1, RF2)
ADF4207 (RF1, RF2)
9
ADF4208 (RF1)
ADF4208 (RF1)
ADF4208 (RF1)
10
ADF4208 (RF2)
Spurious Signals
RF1, RF2
(20 kHz Loop B/W)
RF1, RF2 (1 kHz Loop B/W)
–169
–171
–173
–160
–162
–164
–169
–171
–173
–160
–162
–164
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 25 kHz PFD Frequency
@ 25 kHz PFD Frequency
@ 25 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ 200 kHz PFD Frequency
@ VCO Output
@ 540 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
@ 836 MHz, 30 kHz at PFD
@ 1750 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
@ 1750 MHz Output, 200 kHz at PFD
@ 900 MHz Output, 200 kHz at PFD
–92
–90
–81
–85
–91
–66
–89
–92
–90
–81
–85
–91
–66
–89
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
–80/–84
–65/–73
–80/–84
–65/–73
dB typ
dB typ
@ 200 kHz/400 kHz and 200 kHz PFD
@10 kHz/20 kHz and 10 kHz PFD
NOTES
Operating temperature range is as follows: B Version: –40
°
C to +85
°
C.
2
The B Chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is
less than this value.
4
V
1 = V
2 = 3 V; For V
1 = V
2 = 5 V, use CMOS-compatible levels.
5
Guaranteed by design. Sample tested to ensure compliance.
6
Typical values apply for V
DD
= 3 V; P = 32; RF1
IN
1/RF2
IN
2 for ADF4206 = 540 MHz; RF1
IN
1/RF2
IN
2 for ADF4207 = 900 MHz; RF1
IN
1/RF2
IN
2 for ADF4208 = 900 MHz.
7
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value).
8
The phase noise is measured at a 1 kHz unless otherwise noted. The phase noise is measured with the EVAL-ADF4206/ADF4207EB or the EVAL-AD4208EB Evaluation
Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f
= 10 MHz @ 0 dBm).
9
f
REFIN
= 10 MHz; f
PFD
= 30 kHz; Offset Frequency = 300 Hz; f
RF/IF
= 836 MHz; N = 27866; Loop B/W = 3 kHz.
10
f
REFIN
= 10 MHz; f
PFD
= 10 kHz; Offset Frequency = 200 Hz; f
RF
= 1750 MHz; N = 175000; Loop B/W = 1 kHz.
Specifications subject to change without notice.
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| ADF4206BRU | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual 16-Pin TSSOP |
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