參數(shù)資料
型號: ADF4213BCPZ-REEL7
廠商: ANALOG DEVICES INC
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 3000 MHz, QCC20
封裝: CSP-20
文件頁數(shù): 12/20頁
文件大?。?/td> 252K
代理商: ADF4213BCPZ-REEL7
REV. A
–2–
ADF4210/ADF4211/ADF4212/ADF4213–SPECIFICATIONS1
(VDD1 = VDD2 = 3 V
10%, 5 V
10%; VDD1, VDD2
≤ VP1, VP2 ≤ 6.0 V; AGNDRF = DGNDRF = AGNDIF = DGNDIF = 0 V; RSET = 2.7 k dBm to 50 ;
TA = TMIN to TMAX unless otherwise noted.)
Parameter
B Version
B Chips
2
Unit
Test Conditions/Comments
RF/IF CHARACTERISTICS (3 V)
RF Input Frequency (RFIN)
See Figure 3 for Input Circuit.
ADF4210
0.1/1.2
GHz min/max
Use a square wave for frequencies lower than FMIN.
ADF4211
0.1/2.0
GHz min/max
ADF4212
0.15/2.7
GHz min/max
ADF4213
0.2/3.0
GHz min/max
RF Input Sensitivity
–10/0
dBm min/max
IF Input Frequency (IFIN)
ADF4210
60/550
MHz min/max
ADF4211
60/550
MHz min/max
ADF4212
0.06/1.0
GHz min/max
ADF4213
0.06/1.0
GHz min/max
IF Input Sensitivity
–10/0
dBm min/max
Maximum Allowable
Prescaler Output Frequency
3
165
MHz max
RF/IF CHARACTERISTICS (5 V)
RF Input Frequency (RFIN)
See Figure 3 for Input Circuit.
ADF4210
0.18/1.2
GHz min/max
Use a square wave for frequencies lower than FMIN.
ADF4211
0.18/2.0
GHz min/max
ADF4212
0.2/2.3
GHz min/max
ADF4213
0.2/2.5
GHz min/max
RF Input Sensitivity
–5/0
dBm min/max
IF Input Frequency (IFIN)
ADF4210
100/550
MHz min/max
ADF4211
100/550
MHz min/max
ADF4212
0.1/1.0
GHz min/max
ADF4213
0.1/1.0
GHz min/max
IF Input Sensitivity
–5/0
dBm min/max
Maximum Allowable
Prescaler Output Frequency
3
200
MHz max
REFIN CHARACTERISTICS
See Figure 2 for Input Circuit.
REFIN Input Frequency
0/115
MHz min/max
For F < 5 MHz, use dc-coupled square wave
(0 to VDD ).
REFIN Input Sensitivity
4
–5/0
dBm min/max
AC-Coupled. When dc-coupled, 0 to VDD max
(CMOS-Compatible)
REFIN Input Capacitance
10
pF max
REFIN Input Current
±100
A max
PHASE DETECTOR
Phase Detector Frequency
5
55
MHz max
CHARGE PUMP
ICP Sink/Source
Programmable: See Table V
High Value
5
mA typ
With RSET = 2.7 k
Low Value
625
A typ
Absolute Accuracy
3
% typ
With RSET = 2.7 k
RSET Range
1.5/5.6
k
, min/max
ICP Three-State Leakage Current
1
nA typ
Sink and Source Current Matching
2
% typ
0.5 V
VCP
VP – 0.5 V
ICP vs. VCP
2
% typ
0.5 V
VCP
VP – 0.5 V
ICP vs. Temperature
2
% typ
VCP = VP/2
LOGIC INPUTS
VINH, Input High Voltage
0.8
× DV
DD
0.8
× DV
DD
V min
VINL, Input Low Voltage
0.2
× DV
DD
0.2
× DV
DD
V max
IINH/IINL, Input Current
±1
A max
CIN, Input Capacitance
10
pF max
LOGIC OUTPUTS
VOH, Output High Voltage
DVDD – 0.4
V min
IOH = 500
A
VOL, Output Low Voltage
0.4
V max
IOL = 500
A
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