dBc
參數(shù)資料
型號(hào)： ADF4213BRU-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/20頁(yè)
文件大小： 0K
描述： IC PLL FREQ SYNTHESIZER 20-TSSOP
產(chǎn)品變化通告： ADF4213,16 Discontinuation 15/May/2012
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 時(shí)鐘/頻率合成器（RF/IF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 3:1
差分 - 輸入:輸出： 是/無(wú)
頻率 - 最大： 3GHz
除法器/乘法器： 無(wú)/無(wú)
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 20-TSSOP
包裝： 帶卷 (TR)
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–9–
TEMPERATURE – C
100
–40
0
20
40
60
80
–100
FIRST
REFERENCE
SPUR
–
dBc –70
–80
–90
–60
–20
VDD = 3V
VP = 5V
TPC 19. ADF4213 Reference Spurs vs. Temperature
(836 MHz, 30 kHz, 3 kHz)
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown below in Figure 2. SW1 and
SW2 are normally-closed switches. SW3 is normally-open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
on power-down.
BUFFER
TO R COUNTER
REFIN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
NC = NO CONNECT
Figure 2. Reference Input Stage
RF/IF INPUT STAGE
The RF/IF input stage is shown in Figure 3. It is followed by a
2-stage limiting amplier to generate the CML (Current Mode
Logic) clock levels needed for the prescaler.
AVDD
AGND
2k
1.6V
BIAS
GENERATOR
RFINA
RFINB
Figure 3. RF/IF Input Stage
PRESCALER (P/P + 1)
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler, operating at CML
levels, takes the clock from the RF/IF input stage and divides
it down to a manageable frequency for the CMOS A and B
counters in the RF and If sections. The prescaler in both
sections is programmable. It can be set in software to 8/9, 16/17,
32/33, or 64/65. See Tables IV and VI. It is based on a syn-
chronous 4/5 core.
RF/IF A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The counters are specied to work when the
prescaler output is 200 MHz or less, when VDD = 5 V. Typically,
they will work with 250 MHz output from the prescaler. Thus,
with an RF input frequency of 2.5 GHz, a prescaler value of
16/17 is valid, but a value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual modulus
prescaler make it possible to generate output frequencies which
are spaced only by the Reference Frequency divided by R. The
equation for the VCO frequency is as follows:
fVCO = [(P
× B) + A] × f
REFIN/R
fVCO = Output Frequency of external voltage controlled
oscillator (VCO).
P
= Preset modulus of dual modulus prescaler (8/9,
16/17, etc.).
B
= Preset Divide Ratio of binary 13-bit counter
(3 to 8191).
A
= Preset Divide Ratio of binary 6-bit A counter
(0 to 63).
fREFIN = External reference frequency oscillator.
R
= Preset divide ratio of binary 15-bit programmable refer-
ence counter (1 to 32767).
13-BIT B-
COUNTER
5-BIT A-
COUNTER
PRESCALER
P/P + 1
FROM RF
INPUT STAGE
MODULUS
CONTROL
N = BP + A
LOAD
TO PFD
Figure 4. RF/IF A and B Counters
RF/IF COUNTER
The 15-bit RF/IF R counter allows the input reference fre-
quency to be divided down to product the input clock to the
phase frequency detector (PFD). Division ratios from 1 to
32767 are allowed.
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