參數(shù)資料
型號: ADG5434BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 11/24頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 20TSSOP
標(biāo)準(zhǔn)包裝: 75
功能: 開關(guān)
電路: 4 x SPDT - NC/NO
導(dǎo)通狀態(tài)電阻: 16 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 9 V ~ 40 V,±9 V ~ ±22 V
電流 - 電源: 80µA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 20-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-TSSOP
包裝: 管件
Data Sheet
ADG5433/ADG5434
Rev. C | Page 19 of 24
TRENCH ISOLATION
In the ADG5433/ADG5434, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and the
result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
Figure 36. Trench Isolation
09207-
032
NMOS
PMOS
P-WELL
N-WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
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