VP = 5 V, VN = 0 V, TA = 25°C, R
參數(shù)資料
型號： ADL5310ACPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 14/20頁
文件大小： 0K
描述： IC CONV DUAL LOGARITHMIC 24LFCSP
設(shè)計資源： Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056)
Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
標(biāo)準(zhǔn)包裝： 1
類型： 對數(shù)轉(zhuǎn)換器
應(yīng)用： 光纖
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 24-LFCSP-VQ（4x4）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 772 (CN2011-ZH PDF)
其它名稱： ADL5310ACPZ-REEL7DKR
ADL5310
Rev. A | Page 3 of 20
SPECIFICATIONS
VP = 5 V, VN = 0 V, TA = 25°C, RREF = 665 k, and VRDZ connected to VREF, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
INPUT INTERFACE
Pins 1 to 6: INP1 and INP2, IRF1 and IRF2, VSUM
Specified Current Range, IPD
Flows toward INP1 pin or INP2 pin
3 n
3 m
A
Input Current Min/Max Limits
Flows toward INP1 pin or INP2 pin
10 m
A
Reference Current, IREF, Range
Flows toward IRF1 pin or IRF2 pin
3 n
3 m
A
Summing Node Voltage
Internally preset; user alterable
0.46
0.5
0.54
V
Temperature Drift
–40°C < TA < +85°C
0.030
mV/°C
Input Offset Voltage
VIN
VSUM, VIREF VSUM
20
+20
mV
LOGARITHMIC OUTPUTS
Pin 15 and Pin 16: LOG1 and LOG2
Logarithmic Slope
190
200
210
mV/dec
–40°C < TA < +85°C
185
215
mV/dec
Logarithmic Intercept1
165
300
535
pA
–40°C < TA < +85°C
40
1940
pA
Law Conformance Error
10 nA < IPD < 1 mA
0.1
0.4
dB
3 nA < IPD < 3 mA
0.3
0.6
dB
Wideband Noise2
IPD > 3 A; output referred
0.5
V/√Hz
Small Signal Bandwidth
IPD = 3 A
1.5
MHz
Maximum Output Voltage
1.7
V
Minimum Output Voltage
Limited by VN = 0 V
0.10
V
Output Resistance
4.375
5
5.625
k
REFERENCE OUTPUT
Pin 7 and Pin 24 (internally shorted): VREF
Voltage wrt Ground
2.45
2.5
2.55
V
–40°C < TA < +85°C
2.42
2.58
V
Maximum Output Current
Sourcing (grounded load)
20
mA
Incremental Output Resistance
Load current < 10 mA
4
OUTPUT BUFFERS
Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1,
and OUT1
Input Offset Voltage
20
+20
mV
Input Bias Current
Flowing out of Pins 13, 14, 17, and 18
0.4
A
Incremental Input Resistance
35
M
Incremental Output Resistance
Load current < 10 mA; gain = 1
0.5
Output High Voltage
RL = 1 k to ground
VP
0.1
V
Output Low Voltage
RL = 1 k to ground
0.10
V
Peak Source/Sink Current
30
mA
Small-Signal Bandwidth
Gain = 1
15
MHz
Slew Rate
0.2 V to 4.8 V output swing
15
V/s
POWER SUPPLY
Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG
Positive Supply Voltage
(VP – VN ) ≤ 12 V
3
5
12
V
Quiescent Current
Input currents < 10 A
9.5
11.5
mA
Negative Supply Voltage (Optional)
(VP – VN ) ≤ 12 V
5.5
0
V
1 Other values of logarithmic intercept can be achieved by adjustment of RREF.
2 Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.
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