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| 型號： | ADL5310ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CONV DUAL LOGARITHMIC 24LFCSP |
| 設(shè)計資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 772 (CN2011-ZH PDF) |
| 其它名稱： | ADL5310ACPZ-REEL7DKR |
ADL5310
Rev. A | Page 5 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24
1
2
3
4
5
6
18
17
16
15
14
13
23
22
21
20
19
7
8
9
10
11
12
PIN 1
INDICATOR
TOP VIEW
(Not to Scale)
ADL5310
DUAL LOG AMP
VSUM
INP1
IRF1
IRF2
INP2
VSUM
SCL1
BIN1
LOG1
LOG2
BIN2
SCL2
04415-0-002
VR
EF
V
RDZ
COM
M
COM
M
VN
EG
OUT1
VR
EF
VPOS
VN
EG
VN
EG
OUT2
Figure 2. 24-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Function
1, 6
VSUM
Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input
summing node potentials. Pin 1 and Pin 6 are internally shorted.
2
INP1
Channel 1 Numerator Input. Accepts (sinks) photodiode current IPD1. Usually connected to photodiode anode
such that photocurrent flows into INP1.
3
IRF1
Channel 1 Denominator Input. Accepts (sinks) reference current, IRF1.
4
IRF2
Channel 2 Denominator Input. Accepts (sinks) reference current, IRF2.
5
INP2
Channel 2 Numerator Input. Accepts (sinks) photodiode current IPD2. Usually connected to photodiode anode
such that photocurrent flows into INP2.
7, 24
VREF
Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted.
8, 9
VPOS
Positive Supply, (VP – VN) ≤ 12 V. Both pins must be connected externally.
10, 11, 20
VNEG
Optional Negative Supply, VN. These pins are usually grounded. For more details, see the General Structure and
Applications sections. All VNEG pins must be connected externally.
12
OUT2
Buffer Output for Channel 2.
13
SCL2
Buffer Amplifier Inverting Input for Channel 2.
14
BIN2
Buffer Amplifier Noninverting Input for Channel 2.
15
LOG2
Output of the Logarithmic Front End for Channel 2.
16
LOG1
Output of the Logarithmic Front End for Channel 1.
17
BIN1
Buffer Amplifier Noninverting Input for Channel 1.
18
SCL1
Buffer Amplifier Inverting Input for Channel 1.
19
OUT1
Buffer Output for Channel 1.
21, 22
COMM
Analog Ground. Pin 21 and Pin 22 are internally shorted.
23
VRDZ
Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the
intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be
provided.
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| ADL5310-EVAL | 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD, 120DB RANGE (3 NA TO 3 MA) DUAL LOGARITH - Bulk |
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