ADM1490E/ADM1491E
Data Sheet
Rev. D | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
07430-
034
VCC 1
RO
2
DI
3
GND
4
A
8
B
7
Z
6
Y
5
ADM1490E
TOP VIEW
(Not to Scale)
Figure 7. 8-Lead MSOP and 8-Lead SOIC
Pin Configuration
07430-
013
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. PIN 7 IS NOT CONNECTED INTERNALLY.
SHOWN AS GND TO COMPLY WITH
INDUSTRY STANDARD PINOUT.
3. PIN 14 IS NOT CONNECTED INTERNALLY.
SHOWN AS VCC TO COMPLY WITH
INDUSTRY STANDARD PINOUT.
NC
1
RO
2
RE
3
DE
4
VCC
14
VCC
13
A
12
B
11
DI
5
Z
10
GND 6
Y
9
GND 7
NC
8
ADM1491E
TOP VIEW
(Not to Scale)
Figure 8. 14-Lead, Narrow Body SOIC
Pin Configuration
RO
1
RE
2
DE
3
DI
4
GND
5
VCC
10
A
9
B
8
Z
7
Y
6
ADM1491E
TOP VIEW
(Not to Scale)
07430-
015
Figure 9. 10-Lead MSOP
Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
8-Lead SOIC,
8-Lead MSOP
14-Lead SOIC
10-Lead MSOP
1
NC
No Connect. This pin is available on the 14-lead SOIC only.
2
1
RO
Receiver Output.
N/A1
3
2
RE
Receiver Output Enable. A low level enables the receiver output, whereas
a high level places the receiver output in a high impedance state.
N/A1
4
3
DE
Driver Output Enable. A logic high enables the differential driver outputs,
A and B, whereas a logic low places the differential driver outputs in a
high impedance state.
3
5
4
DI
Driver Input. When the driver is enabled, a logic low on DI forces Pin A low
and Pin B high, whereas a logic high on DI forces Pin A high and Pin B low.
4
6
5
GND
Ground.
7
GND
Ground. This pin is available on the 14-lead SOIC only.
8
NC
No Connect. This pin is available on the 14-lead SOIC only.
5
9
6
Y
Noninverting Driver Output Y.
6
10
7
Z
Inverting Driver Output Z.
7
11
8
B
Inverting Receiver Input B.
8
12
9
A
Noninverting Receiver Input A.
1
13
10
VCC
Power Supply (5 V ± 5%).
N/A1
14
N/A1
VCC
Power Supply (5 V ± 5%). This pin is available on the 14-lead SOIC only.
1
N/A indicates not applicable.