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參數(shù)資料
| 型號： | ADN2525ACPZ-WP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, MO-220VEED-2, LFCSP-16 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ADN2525ACPZ-WP |
ADN2525
LOAD MIS-TERMINATION
Due to its excellent S22 performance, the ADN2525 can drive
differential loads that range from 5 to 50 . In practice, many
TOSAs have differential resistance less than 50 . In this case,
with 50 differential transmission lines connecting the
ADN2525 to the load, the load end of the transmission lines are
mis-terminated. This mis-termination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2525 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to be
achieved, even when the load end of the transmission lines is
significantly mis-terminated. The connection between the load
and the ADN2525 must be made with 50 differential (25
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
Rev. 0 | Page 12 of 16
POWER CONSUMPTION
The power dissipated by the ADN2525 is given by
IBIAS
V
I
V
13
VCC
P
IBIAS
SUPPLY
MSET
5
×
+
+
×
=
where:
VCC
is the power supply voltage.
IBIAS
is the bias current generated by the ADN2525.
V
MSET
is the voltage applied to the MSET pin.
I
SUPPLY
is the sum of the current that flows into the VCC,
IMODP, and IMODN pins of the ADN2525 when
IBIAS = IMOD = 0 expressed in amps (see Table 1).
V
IBIAS
is the average voltage on the IBIAS pin.
Considering
V
BSET
/IBIAS
= 10 as the conversion factor from
V
BSET
to
IBIAS
, the dissipated power becomes
IBIAS
V
BSET
V
10
SUPPLY
MSET
V
13
I
VCC
P
×
+
+
×
=
5
To ensure long-term reliable operation, the junction tempera-
ture of the ADN2525 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the module’s case can be
used as heat sink as shown in Figure 31. A compact optical
module is a complex thermal environment, and calculations of
device junction temperature using the package θ
JA
(junction-to-
ambient thermal resistance) do not yield accurate results.
0
T
TOP
T
J
TPAD
DIE
PACKAGE
THERMAL COMPOUND
MODULE CASE
PCB
VIAS
COPPER PLANE
THERMO-COUPLE
Figure 31. Typical Optical Module Structure
The following procedure can be used to estimate the IC
junction temperature:
T
TOP
= Temperature at top of package in °C.
T
PAD
= Temperature at package exposed paddle in °C.
T
J
= IC junction temperature in °C.
P
= Power dissipation in W.
θ
J-TOP
= Thermal resistance from IC junction to package top.
θ
J-PAD
= Thermal resistance from IC junction to package exposed
pad.
T
TOP
0
P
θ
J-TOP
T
PAD
T
TOP
θ
J-PAD
T
PAD
Figure 32. Electrical Model for Thermal Calculations
T
TOP
and T
PAD
can be determined by measuring the temperature
at points inside the module as shown in Figure 31. The thermo-
couples should be positioned to obtain an accurate measurement
of the package top and paddle temperatures. Using the model
shown in Figure 32, the junction temperature can be calculated
using the following formula:
(
TOP
J
PAD
J
J
T
θ
where θ
J-TOP
and θ
J-PAD
are given in Table 2 and
P
is the power
dissipated by the ADN2525.
)
TOP
J
PAD
J
TOP
J
PAD
T
PAD
J
TOP
T
P
θ
+
θ
×
+
θ
×
+
θ
×
θ
×
=
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