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參數(shù)資料
| 型號： | ADN2815ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA REC 1.25GBPS 32LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
Data Sheet
ADN2815
Rev. C | Page 19 of 24
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. The
VEE pins should be soldered directly to the ground plane to
reduce series inductance. If the ground plane is an internal
plane and connections to the ground plane are made through
vias, multiple vias can be used in parallel to reduce the series
inductance, especially on Pin 23, which is the ground return for
the output buffers. The exposed pad should be connected to the
GND plane using plugged vias so that solder does not leak
through the vias during reflow.
Use of a 22 F electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 F and 1 nF ceramic chip capacitors, they
should be placed between the IC power supply VCC and VEE,
as close as possible to the ADN2815 VCC pins.
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 19 for the
recommended connections.
By using adjacent power supply and GND planes, excellent high
frequency decoupling can be realized by using close spacing
between the planes. This capacitance is given by
( )
pF
ε
.
A/d
C
r
PLANE
88
0
=
where:
εris the dielectric constant of the PCB material.
A is the area of the overlap of power and GND planes (cm2).
d is the separation between planes (mm).
For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2.
50 TRANSMISSION LINES
DATAOUTP
DATAOUTN
CLKOUTP
CLKOUTN
0.1F
22F
1nF
0.1F
0.47F ±20%
>300M INSULATION RESISTANCE
1nF
0.1F
1nF
+
VCC
50
OPTICAL
TRANSCEIVER
MODULE
VCC
NC
C
I2C CONTROLLER
VCC
04952-
0-
031
1
VCC
2
VCC
3
VREF
4
NIN
5
PIN
6
NC
7
NC
8
VEE
24
VCC
23
VEE
22
NC
21
SDA
20
SCK
19
SADDR5
18
VCC
17
VEE
9
10
RE
F
CL
K
P
1
RE
F
CL
KN
12
V
CC
13
VEE
14
CF
2
15
CF
1
16
LO
L
32
V
CC
31
V
CC
30
VEE
29
D
AT
AO
UT
P
28
D
AT
AO
UT
N
27
S
Q
UE
L
CH
26
CL
KO
UT
P
25
CL
KO
UT
N
EXPOSED PAD
TIED OFF TO
VEE PLANE
WITH VIAS
Figure 19. Typical ADN2815 Applications Circuit
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