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參數(shù)資料
| 型號： | ADN2815ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA REC 1.25GBPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
ADN2815
Data Sheet
Rev. C | Page 14 of 24
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
The ADN2815 acquires frequency from the data over a range of
data frequencies from 10 Mb/s to 1.25 Gb/s. The lock detector
circuit compares the frequency of the VCO and the frequency
of the incoming data. When these frequencies differ by more
than 1000 ppm, LOL is asserted. This initiates a frequency
acquisition cycle. The VCO frequency is reset to the bottom of
its range, which is 10 MHz. The frequency detector then
compares this VCO frequency and the incoming data frequency
and increments the VCO frequency, if necessary. Initially, the
VCO frequency is incremented in large steps to aid fast acquisi-
tion. As the VCO frequency approaches the data frequency, the
step size is reduced until the VCO frequency is within 250 ppm
of the data frequency, at which point LOL is deasserted.
Once LOL is deasserted, the frequency-locked loop is turned
off. The PLL/DLL pulls in the VCO frequency the rest of the
way until the VCO frequency equals the data frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 14 and Pin 15. A 0.47 F ± 20%, X7R ceramic
chip capacitor with < 10 nA leakage current is recommended.
Leakage current of the capacitor can be calculated by dividing
the maximum voltage across the 0.47 F capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 F capacitor should be greater than 300 M.
INPUT BUFFER
The input buffer has differential inputs (PIN/NIN), which are
internally terminated with 50 to an on-chip voltage reference
(VREF = 2.5 V typically). The minimum differential input level
required to achieve a BER of 1010 is 200 mV p-p.
LOCK DETECTOR OPERATION
The lock detector on the ADN2815 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2815 is a continuous rate CDR that
locks onto any data rate from 10 Mb/s to 1.25 Gb/s without the
use of a reference clock as an acquisition aid. In this mode, the
lock detector monitors the frequency difference between the
VCO and the input data frequency, and deasserts the loss-of-
lock signal, which appears on Pin 16 (LOL), when the VCO is
within 250 ppm of the data frequency. This enables the D/PLL,
which pulls the VCO frequency in the remaining amount and
acquires phase lock. Once locked, if the input frequency error
exceeds 1000 ppm (0.1%), the loss-of-lock signal is reasserted
and control returns to the frequency loop, which begins a new
frequency acquisition starting at the lowest point in the VCO
operating range, 10 MHz. The LOL pin remains asserted until
the VCO locks onto a valid input data stream to within
250 ppm frequency error. This hysteresis is shown in Figure 15.
04952-0-020
LOL
0
–250
250
1000
fVCO ERROR
(ppm)
–1000
1
Figure 15. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In REFCLK mode, a reference clock is used as an acquisition aid
to lock the ADN2815 VCO. Lock-to-reference mode is enabled
by setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss-of-lock signal, which appears on Pin 16 (LOL), is
deasserted when the VCO is within 250 ppm of the desired
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss-of-lock
signal is reasserted and control returns to the frequency loop,
which reacquires with respect to the reference clock. The LOL
pin remains asserted until the VCO frequency is within
250 ppm of the desired frequency. This hysteresis is shown in
Static LOL Mode
The ADN2815 implements a static LOL feature, which indicates
if a loss-of-lock condition has ever occurred and remains
asserted, even if the ADN2815 regains lock, until the static LOL
bit is manually reset. The I2C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss-of-lock
condition, this bit is internally asserted to logic high. The
MISC[4] bit remains high even after the ADN2815 has
reacquired lock to a new data rate. This bit can be reset by
writing a 1 followed by 0 to I2C Register Bit CTRLB[6]. Once
reset, the MISC[4] bit remains deasserted until another loss-of-
lock condition occurs.
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph.
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