參數(shù)資料
型號: ADN2850ACP25-RL7
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字電位計
英文描述: Nonvolatile Memory, Dual 1024 Position Programmable Resistors
中文描述: DUAL 25K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, QCC16
封裝: 5 X 5 MM, LFCSP-16
文件頁數(shù): 14/18頁
文件大?。?/td> 270K
代理商: ADN2850ACP25-RL7
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Programmable Resistors
ADN2850
REV PrH, 13, AUG 2001
14
APPLICATIONS
Optical Transmitter Calibration with ADN2841
Together with the multi-rate 2.7Gbps Laser Diode Driver
ADN2841, the ADN2850 forms an optical supervisory system
where the dual programmable resistors can be used to set the
laser average optical power and extinction ratio, see Figure 13.
ADN2850 is particularly ideal for the optical parameter settings
because of its high resolution and superior temperature
coefficient characteristics.
The ADN2841 is a 2.7 Gbps laser diode driver that utilizes a
unique control algorithm to manage both the laser average
power and extinction ratio after the laser initial factory
calibration. It stabilizes the laser data transmission by
continuously monitoring its optical power, and correcting the
variations caused by temperature and the laser degradation over
time. In ADN2841, the I
MPD
monitors the laser diode current.
Through its dual loop Power and Extinction Ratio control,
calibrated by ADN2850, the internal driver controls the bias
current I
BIAS
and consequently the average power. It also
regulates the modulation current, I
MODP
by changing the
modulation current linearly with slope efficiency. Any changes
in the laser threshold current or slope efficiency are therefore
compensated. As a result, this optical supervisory system
minimizes the laser characterization efforts and therefore
enables designers to apply comparable lasers provided from
multiple sources.
IMODP
BIAS
PSET
ERSET
CS
CLK
SDI
E2MEM
IMPD
VCC
VCC
ADN2841
C
E2MEM
ADN2850
DIN
DINQ
IDTONE
D
D
I
RDAC1
W1
B1
RDAC2
W2
B2
Figure 13. Optical Supervisory System
Incoming Optical Power Monitoring
ADN2850 comes with a pair of matched diode-connected PNPs,
Q
1
and Q
2
, which can be used to configure an incoming optical
power monitoring function. Figure 14 shows such conceptual
circuit. With a reference current source, an instrumentation
amplifier, and a logarithmic amplifier, this feature can be used to
monitor the optical power by knowing the DC average photo
diode current from the following properties:
IPD
IREF
Post
LPF
0.75 Bit Rate
CDR
Data
Clock
RFB
V1
V2
Q1
Q2
RG
(1+100k/RG)*(V2- V1)
AD623
In Amp
Log Amp
Log (Average Power)
TIA
Figure 14. Conceptual Incoming Optical Power Monitoring
Circuit.
1
1
ln
1
1
S
I
I
C
I
T
V
BE
V
V
=
=
(2)
2
2
ln
2
2
S
I
C
T
V
BE
V
V
=
=
(3)
Note I
C1
=
α
1
*I
PD
, I
C2
=
α
2
*I
REF
. Since Q
1
and Q
2
are matched,
therefore
α
1
equals
α
2
and I
S1
equals I
S2
. Combining equations 2
and 3 yields
)
ln(
2
1
REF
I
PD
I
T
V
-V
V
=
(4)
Where I
S1
and I
S2
are saturation current
V
1,
V
2
are V
BE
, base-emitted voltages of the diode-connector transistors
V
T
is the thermal voltage which is equal to k*T/q. V
T
=26mV at 25
C
k = Boltzmann’s constant = 1.38E-23 joules/kelvin
q = electron charge = 1.6E-19 coulomb
T = temperature in kelvin
I
PD
= photo diode current
I
REF
= reference current
With the final logarithmic amplification, the output voltage
represents the average incoming optical power. The output
voltage of the log stage does not have to be accurate from device
to device as the responsivity of the photo diode will change.
However, temperature compensation and the aging stability of
the photo diode may be required. The user may also calibrate the
log amp using two values of input optical power to give an
offset and gradient values. This negates the need for a true log
base 10 conversion.
Resistance Scaling
ADN2850 offers either 25K
or 250K
full scale resistance.
For users who need lower resistance and still maintain the
numbers of step adjustment, they can parallel multiple devices.
Figure 15 shows a simple scheme of paralleling both channel of
the RDACs. In order to adjust half of the resistance linearly per
step, users need to program the RDACs coherently with the
same settings and tie the terminals as shown. Much lower
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