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參數(shù)資料
| 型號： | ADN2850ACP25-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字電位計(jì) |
| 英文描述： | Nonvolatile Memory, Dual 1024 Position Programmable Resistors |
| 中文描述： | DUAL 25K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, QCC16 |
| 封裝： | 5 X 5 MM, LFCSP-16 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 270K |
| 代理商： | ADN2850ACP25-RL7 |
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Programmable Resistors
6dB step increment and decrement are achieved by shifting the
bit internally to the left and right respectively. The following
information explains the nonideal ±6dB step adjustment at
certain conditions. Table 3 illustrates the operation of the
shifting function on the individual RDAC register data bits.
Each line going down the table represents a successive shift
operation. Note that the left shift #12 & #13 commands
were
modified such that if the data in the RDAC register is equal to
zero, and the data is left shifted, the RDAC register is then set to
code 1. Similary, if the data in the RDAC register is greater than
or equal to mid-scale, and the data is left shifted, then the data in
the RDAC register is automatically set to full-scale. This makes
the left shift function as ideal logarithmic adjustment as is
possible.
The right shift #4 & #5 commands will be ideal only if the LSB
is zero (i.e. ideal logarithmic - no error). If the LSB is a one then
the right shift function generates a linear half LSB error, which
translates to a numbers of bits dependent logarithmic error as
shown in Figure 4. The plot shows the error of the odd numbers
of bits for ADN2850.
ADN2850
REV PrH, 13, AUG 2001
9
Left Shift
00 0000 0000
00 0000 0001
00 0000 0010
00 0000 0100
00 0000 1000
00 0001 0000
00 0010 0000
00 0100 0000
00 1000 0000
01 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
Right Shift
11 1111 1111
01 1111 1111
00 1111 1111
00 0111 1111
00 0011 1111
00 0001 1111
00 0000 1111
00 0000 0111
00 0000 0011
00 0000 0001
00 0000 0000
00 0000 0000
00 0000 0000
Table 3. Detail Left and Right Shift functions for 6dB step increment
and decrement.
Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
Right Shift #4 & #5 command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in Figure 4 shows plots of Log_Error [i.e. 20*log
10
(error/code)] ADN2850. For example, code 3
Log_Error=20*log
10
(0.5/3)=-15.56dB, which is the worst case.
The plot of Log_Error is more significant at the lower codes.
Figure 4. Plot of Log_Error Conformance for Odd Numbers of Bits Only
(Even Numbers of Bits are ideal)
Using Additional internal Nonvolatile EEMEM
The ADN2850 contains additional internal user storage registers
(EEMEM) for saving constants and other 16-bit data. Table 4
provides an address map of the internal storage registers shown
in the functional block diagram as EEMEM1, EEMEM2, and 26
bytes of USER EEMEM.
Address
EEMEM For
0000
RDAC1
a,c
0001
RDAC2
0010
USER1
b
0011
USER2
:
:
1110
USER13
1111
Factory Reserved
Table 4: EEMEM Address Map
NOTES:
a)
RDAC data stored in EEMEM locations are transferred to their
corresponding RDAC REGISTER at Power ON, or when instructions Inst#1,
#8, and
PR
are executed.
USER <data> are internal nonvolatile EEMEM registers available to store
and retrieve constants and other 16-bit information using Inst#3 and Inst#9
respectively.
Execution of instruction #1 leaves the device in the Read Mode power
consumption state. After the last Instruction #1 is executed, the user should
perform a NOP, Instruction #0 to return the device to the low power idling
state.
b)
c)
Daisy Chain Operation
The serial data output pin (SDO) can be used to readout the
content of the wiper settings or EEMEM values under
instructions 10 and 9 respectively. If these instructions are not
used, SDO can be used for daisy chaining multiple devices for
simultaneous operations, see Figure 5. SDO pin contains an
open drain N-Ch FET and requires a pull-up resistor if SDO
function is used. Users need to tie the SDO pin of one package
to the SDI pin of the next package. Users may need to increase
the clock period because the pull-up resistor and the capacitive
loading at the SDO-SDI interface may induce time delay to the
subsequent devices, see Figure 5. If two ADN2850 are daisy
chained, this requires total 48 bits of data. The first 24 bits
(formatted 4-bit instruction, 4-bit address, and 16-bit data) goes
to U2 and the second 24 bits with the same format goes to U1.
The
CS
should be kept low until all 48 bits are clocked into their
respective serial registers. The
CS
is then pulled high to
complete the operation.
Left
Shift
(+6dB/step)
Right
Shift
(-6dB/step)
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