參數(shù)資料
型號(hào)： ADN2850ACP25
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計(jì)
英文描述： Nonvolatile Memory, Dual 1024 Position Programmable Resistors
中文描述： DUAL 25K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, QCC16
封裝： 5 X 5 MM, LFCSP-16
文件頁(yè)數(shù)： 6/18頁(yè)
文件大?。?/td> 270K
代理商： ADN2850ACP25
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Programmable Resistors
ADN2850ACP PIN CONFIGURATION
ADN2850
REV PrH, 13, AUG 2001
6
SDO
2
3
4
12
11
10
9
1
16
15
14
13
5
6
7
8
GND
V
SS
V
1
PR
WP
V
DD
V
2
W1
B1
B2
W2
SDI
CLK RDY
CS
ADN2850ACP PIN DESCRIPTION
#
1
Name
SDO
Description
Serial Data Output Pin. Open Drain Output requires
external pull-up resistor. Commands 9 and 10
activate the SDO output. See Instruction operation
Truth Table. Table 2. Other commands shift out the
previously loaded SDI bit pattern delayed by 24
clock pulses. This allows daisy-chain operation of
multiple packages.
Ground pin, logic ground reference
Negative Supply. Connect to zero volts for single
supply applications.
Log Output Voltage 1 generated from internal diode
configured transistor
Wiper terminal of RDAC1. ADDR(RDAC1) = 0
H
.
B terminal of RDAC1
B terminal of RDAC2.
Wiper terminal of RDAC2. ADDR(RDAC2) = 1
H
.
Log Output Voltage 2 generated from internal diode
configured transistor
Positive Power Supply Pin.
Write Protect Pin. When active low,
WP
prevents
any changes to the present register contents, except
PR
and cmd 1 and 8 will refresh the RDAC register
from EEMEM.
Hardware over ride preset pin. Refreshes the scratch
pad register with current contents of the EEMEM
register. Factory default loads midscale 512
10
until
EEMEM loaded with a new value by the user (
PR
is
activated at the logic high transition).
Serial Register chip select active low. Serial register
operation takes place when
CS
returns to logic high.
Ready. Active-high open drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and
PR.
Serial Input Register clock pin. Shifts in one bit at a
time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time on
positive clock CLK edges. MSB loaded first.
2
3
GND
V
SS
4
V
1
5
6
7
8
9
W1
B1
B2
W2
V
2
10
11
V
DD
WP
12
PR
13
CS
14
RDY
15
CLK
16
SDI
ADN2850ARU PIN CONFIGURATION
CLK
SDI
SDO
GND
V
SS
V
1
W1
B1
RDY
CS
PR
PR
WP
V
DD
V
2
W2
B2
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
ADN2850ARU PIN DESCRIPTION
#
1
Name
CLK
Description
Serial Input Register clock pin. Shifts in one bit at a
time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time on
positive clock CLK edges. MSB loaded first.
Serial Data Output Pin. Open Drain Output requires
external pull-up resistor. Commands 9 and 10
activate the SDO output. See Instruction operation
Truth Table. Table 2. Other commands shift out the
previously loaded SDI bit pattern delayed by 24
clock pulses. This allows daisy-chain operation of
multiple packages
Ground pin, logic ground reference
Negative Supply. Connect to zero volts for single
supply applications.
Log Output Voltage 1 generated from internal diode
configured transistor
Wiper terminal of RDAC1. ADDR(RDAC1) = 0
H
.
B terminal of RDAC1
B terminal of RDAC2.
Wiper terminal of RDAC2. ADDR(RDAC2) = 1
H
.
Log Output Voltage 2 generated from internal diode
configured transistor
Positive Power Supply Pin.
Write Protect Pin. When active low,
WP
prevents
any changes to the present contents except
PR
and
cmd 1 and 8 will refresh the RDAC register from
E2MEM.
Hardware over ride preset pin. Refreshes the scratch
pad register with current contents of the EEMEM
register. Factory default loads midscale 512
10
until
EEMEM loaded with a new value by the user (
PR
is
activated at the logic high transition).
Serial Register chip select active low. Serial register
operation takes place when
CS
returns to logic high.
Ready. Active-high open drain output. Identifies
completion of commands 2, 3, 8, 9, 10, and
PR.
2
SDI
3
SDO
4
5
GND
V
SS
6
V
1
7
8
9
10
11
W1
B1
B2
W2
V
2
12
13
V
DD
WP
14
PR
15
CS
16
RDY
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