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參數(shù)資料
| 型號： | ADN2891ACPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 0K |
| 描述： | IC AMP LIM 16LFCSP |
| 標準包裝： | 1 |
| 放大器類型： | 限制 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分 |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 45mA |
| 電壓 - 電源，單路/雙路(±)： | 2.9 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 95°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 16-LFCSP-VQ |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
| 其它名稱： | ADN2891ACPZ-RL7DKR |
ADN2891
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05244-
002
AVCC 1
THRADJ
5
CAZ1
6
CAZ2
7
LOS
8
PD_CATHOD
E
16
PD_VCC
15
RSSI_OUT
14
SQUELCH
13
PIN 2
TOP VIEW
(Not to Scale)
NIN 3
AVEE 4
DRVCC
12
OUTN
10
DRVEE
9
OUTP
11
ADN2891
Figure 2. Pin Configuration
Note that the LFCSP has an exposed pad on the bottom. To improve heat dissipation, the exposed pad must be soldered to the GND plane
with filled vias.
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
I/O Type
Descriptions
1
AVCC
P
Analog Power Supply.
2
PIN
AI
Differential Data Input, Positive Port, 50 Ω On-Chip Termination.
3
NIN
AI
Differential Data Input, Negative Port, 50 Ω On-Chip Termination.
4
AVEE
P
Analog Ground.
5
THRADJ
AO
LOS Threshold Adjust Resistor.
6
CAZ1
AI
If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
7
CAZ2
AI
If needed, one capacitor can connect between the CAZ1 and CAZ2 pin for
input offset correction.
8
LOS
DO
LOS Detector Output, Open Collector.
9
DRVEE
P
Output Buffer Ground.
10
OUTN
DO
Differential Data Output, CML, Negative Port, 50 Ω On-Chip Termination.
11
OUTP
DO
Differential Data Output, CML, Positive Port, 50 Ω On-Chip Termination.
12
DRVCC
P
Output Buffer Power Supply.
13
SQUELCH
DI
Disable Outputs, 100 kΩ On-Chip Pull-Down Resistor.
14
RSSI_OUT
AO
Average Current Output.
15
PD_VCC
P
Power Input for RSSI Measurement.
16
PD_CATHODE
AO
Photodiode Bias Voltage.
Pad
P
Connect to Ground.
Exposed
Pad
1 P = power; DI = digital input; DO = digital output; AI = analog input; and AO = analog output.
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