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Frame_Capture
Address: 0x13
Access: Read/Write
Reset Value: 0x00
SROM_Enable
Address: 0x14
Access: Write
Reset Value: 0x00
Data Type: Bit field
USAGE: Writing 0x83 to this register will cause the next available complete 1 2/3 frames of pixel
values to be stored to SROM RAM. Writing to this register is required before using the Frame
Capture burst mode to read the pixel values (see the Synchronous Serial Port section for more
details). Writing to this register will stop navigation and cause any firmware loaded in the SROM
to be overwritten. A hardware reset is required to restore navigation, and the firmware must be
reloaded using the SROM Download burst method.
This register can also be used to read the frame capture data. The same data available by reading
the Pixel_Burst register using burst mode is available by reading this register in the normal
fashion. The data pointer is automatically incremented after each read so all 1536 pixel values (1
and 2/3 frames) may be obtained by reading this register 1536 times in a row. Both methods
share the same pointer such that reading pixel values from this register will increment the pointer
causing subsequent reads from the Pixel_Burst register (without initiating a new frame dump) to
start at the current pointer location. This register will return all zeros if read before the frame
capture data is ready. See the Frame Capture description in the Synchronous Serial Port section
for more information.
This register will not retain the last value written. Reads will return zero or frame capture data.
Data Type: 8-bit number.
USAGE: Write to this register to start either SROM download or SROM CRC test.
Write 0x18 to this register before downloading SROM firmware to the SROM_Load register. The
download will not be successful unless this register contains the correct value.
Write 0xA1 to start the SROM CRC test. Wait 7ms plus one frame period , then read result from
the Data_Out_Lower and Data_Out_Upper registers. Navigation is halted and the SPI port should
not be used during this test.
Bit
7
6
5
4
3
2
1
0
Field
FC
7
FC
6
FC
5
FC
4
FC
3
FC
2
FC
1
FC
0
Bit
7
6
5
4
3
2
1
0
Field
SE
7
SE
6
SE
5
SE
4
SE
3
SE
2
SE
1
SE
0
Reserved
Address: 0x15 – 0x18