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| 型號： | ADP5589ACBZ-02-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PORT EXPANDER 19I/O 25WLSCP |
| 產(chǎn)品變化通告： | 8mm Carrier Tape Changes 28/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 系列： | * |
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Data Sheet
ADP5589
Rev. B | Page 41 of 52
RESET1_EVENT_C Register 0x3A
Table 66. RESET1_EVENT_C Bit Descriptions
Bits
Name
R/W
Description
7
RESET1_EVENT_B Level
R/W
Defines which level the third reset event should be.
[6: 0]
RESET1_EVENT_C[6:0]
R/W
Defines an event that can be used to generate the RESET1 signal.
RESET2_EVENT_A Register 0x3B
Table 67. RESET2_EVENT_A Bit Descriptions
Bits
Name
R/W
Description
7
RESET1_EVENT_B Level
R/W
Defines which level the first reset event should be.
For key events:
0 = not applicable; releases not used for reset generation.
1 = press is used as reset event.
For GPIs and logic outputs configured for FIFO updates:
0 = inactive event used as reset condition.
1 = active event used as reset condition.
[6:0]
RESET2_EVENT_A[6:0]
R/W
Defines an event that can be used to generate the RESET2 signal.
Up to two events can be defined for generating the RESET2 signal, using
RESET2_EVENT_A[6:0] and RESET2_EVENT_B[6:0].
If one of the registers is 0, that register is not used for reset generation. All reset events
must be detected at the same time to trigger the reset.
RESET2_EVENT_B Register 0x3C
Table 68. RESET2_EVENT_B Bit Descriptions
Bits
Name
R/W
Description
7
RESET1_EVENT_B Level
R/W
Defines which level the second reset event should be.
[6:0]
RESET2_EVENT_B[6:0]
R/W
Defines an event that can be used to generate the RESET2 signal.
RESET_CFG Register 0x3D
Table 69. RESET_CFG Bit Descriptions
Bits
Name
R/W
Description
7
RESET2_POL
R/W
Sets the polarity of RESET2.
0 = RESET2 is active low.
1 = RESET2 is active high.
6
RESET1_POL
R/W
Sets the polarity of RESET1.
0 = RESET1 is active low.
1 = RESET1 is active high.
5
RST_PASSTHRU_EN
R/W
Allows the RST pin to override (OR with) the RESET1signal.
Function not applicable to RESET2.
[4:2]
RESET_TRIGGER_TIME[2:0]
R/W
Defines the length of time that the reset events must be active before a reset signal is
generated.
All events must be active at the same time for the same duration. Parameter common
to both RESET1 and RESET2.
000 = immediate.
001 = 1.0 sec.
010 = 1.5 sec.
011 = 2.0 sec.
100 = 2.5 sec.
101 = 3.0 sec.
110 = 3.5 sec.
111 = 4.0 sec.
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