參數(shù)資料
型號(hào)： ADP5589ACBZ-02-R7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/52頁(yè)
文件大?。?/td> 0K
描述： IC PORT EXPANDER 19I/O 25WLSCP
產(chǎn)品變化通告： 8mm Carrier Tape Changes 28/Feb/2012
標(biāo)準(zhǔn)包裝： 3,000
系列： *
Data Sheet
ADP5589
Rev. B | Page 17 of 52
LA2_INV
MUX
000
001
SEL[2:0]
OUT
010
011
100
101
110
111
SEL
OUT
0
1
GND
AND2
OR2
XOR2
FF2
IN_LA2
IN_LB2
IN_LC2
(LY1)
LA2
(LY1)
LA2
(IN_LY1)
IN_LA2
SEL
OUT
0
1
AND2
(IN_LY1)
IN_LA2
IN_LB2
IN_LC2
C6_EXTEND_CFG = 1
LOGIC2_SEL
LY1_CASCADE
LA2
LY1
SEL
OUT
0
1
LY2_INV
SEL
OUT
0
1
LY2
LB2_INV
SEL
OUT
0
1
LB2
IN_LB2
LC2_INV
SEL
OUT
0
1
LC2
IN_LC2
FF2_SET
FF2_CLR
SEL
OUT
0
1
OR2
(IN_LY1)
IN_LA2
IN_LB2
IN_LC2
AND
OR
SEL
OUT
0
1
XOR2
FF2
(IN_LY1)
IN_LA2
IN_LB2
IN_LC2
IN_LA2
IN_LB2
IN_LC2
XOR
D
CLR
Q
SET
0
1
SEL
OUT
09714-
021
Figure 22. Logic Block 2
(R3)
PWM_OUT
(C6) PWM_IN
OFF TIME[15:0]
PWM_EN
PWM_IN_AND
PWM_OFFT_LOW_BYTE[7:0]
PWM_MODE
PWM_OFFT_HIGH_BYTE[7:0]
PWM_ONT_LOW_BYTE[7:0]
PWM_ONT_HIGH_BYTE[7:0]
ON TIME[15:0]
PWM
GENERATOR
SEL
OUT
0
1
09714-
022
AND
Figure 23. PWM Block Diagram
PWM BLOCK
The ADP5589 features a PWM generator whose output can be
configured to drive out on I/O Pin R3. PWM on/off times are
programmed via four 8-bit registers.
Newly programmed values are not latched until the final byte,
PWM_ONT_HIGH_BYTE (Address 0x41, Bits[7:0]), is written
The highest frequency obtainable from the PWM is performed
by setting the least significant bit (LSB) of both the on and off
bit patterns, resulting in a 500 kHz signal with a 50% duty cycle.
Each LSB respresents 1 s of on or off time.
The PWM block provides support for continuous PWM
mode as well as a one-shot mode (see Table 74). Additionally,
an external signal can be AND’ed with the internal PWM signal.
This option can be selected by writing a 1 to PWM_IN_AND,
PWM_CFG[2]. The input to the external AND is the C6 I/O
pin. C6 should be set to GPI (GPIO15). Note that the debounce
for C6 will result in a delay of the AND’ing, and can be
controlled using register GPI_15_DEB_DIS (Address 0x28,
Bit[6]).
Newly programmed values are not latched until the final byte,
PWM_ONT_HIGH_BYTE (Address 0x41, Bits[7:0]), is written.
CLOCK DIVIDER BLOCK
The ADP5589 features a clock divider block that divides down
the frequency of an externally supplied source via I/O Pin C6.
The output of the divider is driven out on I/O Pin R3.
CLK_IN
(R3)
CLK_OUT
(C6)
CLK_DIV_EN
CLK_DIV[4:0]
CLK_INV
CLK
DIVIDER
SEL
OUT
0
1
09714-
023
Figure 24. Clock Divider Block
RESET BLOCKS
The ADP5589 features two reset blocks that can generate reset
conditions if certain events are detected at the same time. Up to
three reset trigger events can be programmed for RESET1. Up
to two reset trigger events can be programmed for RESET2. The
event scan control blocks monitor whether these events are present
for the duration of RESET_TRIGGER_TIME[2:0] (0x3D[4:2]).
If they are, reset-initiate signals are sent to the reset generator
blocks. The generated reset signal pulse width is programmable.
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