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參數(shù)資料
| 型號： | ADS1222IPWRG4 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC 24BIT ADC W/2CH MUX 14-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 240 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 2.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，雙極 |
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ADS1222
SBAS314B APRIL 2004 REVISED JANUARY 2009
www.ti.com
11
the buffer will limit the allowable voltage range on
VREFP and VREFN during self or self gain calibration
as the reference pins must remain within the specified
input range of the buffer in order to establish proper gain
calibration.
For best performance, VREF should be VDD/2, but it can
be raised as high as VDD. When VREF exceeds VDD/2,
it is not possible to reach the full-scale digital output
value corresponding to
±2VREF, since this requires the
analog inputs to exceed the power supplies. For
example, if VREF = VDD = 5V, the positive full-scale
signal is 10V. The maximum positive input signal that
can be supplied before the ESD diodes turn on is when
AINP = 5.1V and AINN = –0.1V, resulting in VIN = 5.2V.
Therefore, it is not possible to reach the positive (or
negative) full-scale readings in this configuration. The
digital output codes are limited to approximately one
half of the entire range. For best performance, bypass
the voltage reference inputs with a 0.1
F capacitor
between VREFP and VREFN. Place the capacitor as
close as possible to the pins.
CLOCK INPUT (CLK)
This digital input supplies the system clock to the
ADS1222. The CLK frequency can be increased to
speed up the data rate. CLK must be left running during
normal operation. It may be turned off during Standby
mode to save power, but this is not required. The CLK
input may be driven with 5V logic, regardless of the VDD
voltage.
Minimize the overshoot and undershoot on CLK for the
best analog performance. A small resistor in series with
CLK (10
to 100) can often help. CLK can be
generated from a number of sources including
standalone crystal oscillators and microcontrollers.
DATA READY/DATA OUTPUT (DRDY/DOUT)
This digital output pin serves two purposes. First, it
indicates when new data is ready by going LOW.
Afterwards, on the first rising edge of SCLK, the
DRDY/DOUT pin changes function and begins to
output the conversion data, most significant bit (MSB)
first. Data is shifted out on each subsequent SCLK
rising edge. After all 24 bits have been retrieved, the pin
can be forced high with an additional SCLK. It will then
stay high until new data is ready. This is useful when
polling on the status of DRDY/DOUT to determine when
to begin data retrieval.
SERIAL CLOCK INPUT (SCLK)
This digital input shifts serial data out with each rising
edge. As with CLK, this input may be driven with 5V
logic regardless of the VDD voltage. There is hysteresis
built into this input, but care should still be taken to
ensure a clean signal. Glitches or slow-rising signals
can cause unwanted additional shifting. For this reason,
it is best to make sure the rise-and-fall times of SCLK
are less than 50ns.
FREQUENCY RESPONSE
The ADS1222 frequency response for fCLK = 2MHz is
shown in Figure 20. The frequency response repeats at
multiples of the modulator sampling frequency of
62.5kHz. The overall response is that of a low-pass filter
with a 3db cutoff frequency of 31.5Hz. As shown, the
ADS1222 does a good job attenuating out to 60kHz. For
the best resolution, limit the input bandwidth to less than
this value to keep higher frequency noise from affecting
performance. Often, a simple RC filter on the ADS1222
analog inputs is all that is needed.
Input Frequency (Hz)
Ga
in
(d
B
)
0
20
40
60
80
100
31250
62500
0
Figure 20. Frequency Response
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| ADS1222IPWT | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Conv w/2-Ch Diff Input Mltplxer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1222IPWT | 制造商:Texas Instruments 功能描述:IC 24-BIT ADC 2 CH DIFF I/P MULTI |
| ADS1222IPWTG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Conv w/2-Ch Diff Input Mltplxer RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1224 | 制造商:BB 制造商全稱:BB 功能描述:24-Bit Analog-to-Digital Converter with 4-Channel Differential Input Multiplexer |
| ADS1224EVM | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 ADS1224 Eval Mod RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
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