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參數(shù)資料
| 型號： | ADS1232IPW |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 16/39頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24-BIT 10/80SPS 24-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Basics |
| 視頻文件： | Nuts and Bolts of the Delta-Sigma Converter |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 10，80 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 13.1mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，單極；2 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 889 (CN2011-ZH PDF) |
| 配用： | 296-20803-ND - EVALUATION MODULE FOR ADS1232 |
| 其它名稱： | 296-18589 296-18589-5 296-18589-ND |
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POWER-UP SEQUENCE
AVDD
DVDD
PDWN
m
10 s
POWER-DOWN MODE
DVDD
(1)
Connectto
ADS1232/34
pin
PDWN
1kW
2.2nF
NOTE:(1)AVDDmustbepoweredupatleast
10 sbefore
goeshigh.
m
PDWN
DataReady
Start
Conversion
DRDY/DOUT
SCLK
CLKSoure
Wakeup
Power-DownMode
PDWN
t
13
t
11
t
14
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
When powering up the ADS1232/34, AVDD and
DVDD must be powered up before the PDWN pin
goes high, as shown in Figure 39. If PDWN is not
controlled by a microprocessor, a simple RC delay
circuit must be implemented, as shown in Figure 40.
Figure 39. Power-Up Timing Sequence
Power-Down mode shuts down the entire ADC
circuitry and reduces the total power consumption
close to zero. To enter Power-Down mode, simply
hold the PDWN pin low. Power-Down mode also
resets the entire circuitry to free the ADC circuitry
from locking up to an unknown state. Power-Down
mode can be initiated at any time during readback; it
is not necessary to retrieve all 24 bits of data
beforehand. Figure 41 shows the wake-up timing
from Power-Down mode.
Figure 40. RC Delay Circuit
Figure 41. Wake-Up Timing from Power-Down Mode
SYMBOL
DESCRIPTION
TYP
UNITS
Internal clock
7.95
s
t13
Wake-up time after Power-Down mode
External clock
0.16
s
Crystal oscillator(1)
5.6
ms
t14
(2)
PDWN pulse width
26 (min)
s
(1)
No capacitors on CLKIN/XTAL1 or XTAL2 outputs.
(2)
Value given for fCLK = 4.9152MHz. For different fCLK frequencies, the scale is proportional to the CLK period except for a ±3% variation
when an internal oscillator is used.
Copyright 2005–2008, Texas Instruments Incorporated
23
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ADS1232IPW | 制造商:Texas Instruments 功能描述:IC ADC |
| ADS1232IPW | 制造商:Texas Instruments 功能描述:IC ADC ULTRALOW NOISE 24BIT SMD |
| ADS1232IPW | 制造商:Texas Instruments 功能描述:A/D Converter (A-D) IC |
| ADS1232IPW | 制造商:Texas Instruments 功能描述:IC 24 BIT ADC BRIDGE SENSOR 制造商:Texas Instruments 功能描述:IC, 24 BIT ADC, BRIDGE SENSOR |
| ADS1232IPWG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 24-Bit Ultra Low-Noise RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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