DRDY/DOUT t S ToggledTEMPPinor AbruptChangeinExternalV IN V IN
參數資料
型號： ADS1232IPW
廠商： Texas Instruments
文件頁數： 9/39頁
文件大?。?/td> 0K
描述： IC ADC 24-BIT 10/80SPS 24-TSSOP
產品培訓模塊： Data Converter Basics
視頻文件： Nuts and Bolts of the Delta-Sigma Converter
標準包裝： 60
位數： 24
采樣率（每秒）： 10，80
數據接口： 串行
轉換器數目： 1
功率耗散（最大）： 13.1mW
電壓電源： 模擬和數字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 24-TSSOP
包裝： 管件
輸入數目和類型： 4 個單端，單極；2 個差分，雙極
產品目錄頁面： 889 (CN2011-ZH PDF)
配用： 296-20803-ND - EVALUATION MODULE FOR ADS1232
其它名稱： 296-18589
296-18589-5
296-18589-ND
www.ti.com
SETTLING TIME
A1orA0
t
1
DRDY/DOUT
t
S
ToggledTEMPPinor AbruptChangeinExternalV
IN
V
IN
DRDY/DOUT
Startof
conversion.
1stconversion;
includes
unsettledV .
IN
2ndconversion;
V
settled,but
IN
digitalfilter
unsettled.
3rdconversion;
V
settled,but
IN
digitalfilter
unsettled.
4thconversion;
V
settled,but
IN
digitalfilter
unsettled.
5thconversion;
V
anddigital
IN
filterboth
settled.
Conversion
Time
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
switching input channels. Another example would be
toggling the TEMP pin, which switches the internal
After changing the input multiplexer, the first data are
AINP, AINN signals to connect to either the external
fully settled. In both the ADS1232/4, the digital filter is
AINPx, AINNx pins or to the TEMP diode (see
allowed to settle after toggling either the A1 or A0 pin.
Toggling any of these digital pins will hold the
DRDY/DOUT line high until the digital filter is fully
Note that when settling data, five readings may be
settled. For example, if A0 changes from low to high,
required. If the change in input occurs in the middle
selecting a different input channel, DRDY/DOUT
of the first conversion, four more full conversions of
immediately goes high, and DRDY/DOUT goes low
the fully-settled input are required to get fully-settled
when fully-settled data are ready for retrieval. There
data. Discard the first four readings because they
is no need to discard any data. Figure 32 shows the
contain only partially-settled data.Figure 33 illustrates
timing
of
the
DRDY/DOUT
line
as
the
input
the settling time for the ADS1232/4 in Continuous
multiplexer changes.
Conversion mode.
In certain instances, large and/or abrupt changes in
input will require four data cycles to settle. One
example of such a change would be an external
multiplexer in front of the ADS1232/4, which can
cause large changes in input voltage simply by
Figure 32. Example of Settling Time After Changing the Input Multiplexer
SYMBOL
DESCRIPTION(1)
MIN
MAX
UNITS
tS
Setup time for changing the A1 or A0 pins
40
50
s
SPEED = 1
51
ms
Settling time (DRDY/DOUT
t1
held high)
SPEED = 0
401
ms
(1)
Values given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
Figure 33. Settling Time in Continuous Conversion Mode
Copyright 2005–2008, Texas Instruments Incorporated
17
Product Folder Link(s): ADS1232 ADS1234
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