參數(shù)資料
型號(hào): ADS5510
英文描述: 11-Bit, 125-MSPS Analog-To-Digital Converter
中文描述: 11位,125 MSPS的模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 18/29頁(yè)
文件大?。?/td> 835K
代理商: ADS5510
www.ti.com
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5510 is a low-power, 11-bit, 125 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a
single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline every half clock cycle. This process results in a data
latency of 17.5 clock cycles, after which the output data is available as a 11-bit parallel word, coded in either
straight offset binary or binary two's complement format.
INPUT CONFIGURATION
The analog input for the ADS5510 consists of a differential sample-and-hold architecture implemented using the
switched capacitor technique shown in
Figure 24
.
R
3
R
1a
L
1
L
2
R
1b
C
1a
C
1b
C
A
CP
1
CP
3
VINCM
1V
CP
4
CP
2
INP
INM
S
3a
S
3b
S
2
S
1a
S
1b
L
1
, L
2
: 6 nH 10 nH effective
R
1a
, R
1b
: 5 8
C
1a
, C
1b
: 2.2 pF 2.6 pF
CP
1
, CP
2
: 2.5 pF 3.5 pF
CP
, CP
: 1.2 pF 1.8 pF
C
A
: 0.8 pF 1.2 pF
R
: 80 120
Swithches: S
, S
On Resistance: 35 50
S
2
: On Resistance: 7.5 15
S
, S
: On Resistance: 40 60
All switches OFF Resistance: 10 G
ADS5510
SLAS499–JANUARY 2007
A.
All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 24. Analog Input Stage
18
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