參數(shù)資料
型號(hào): ADS5510
英文描述: 11-Bit, 125-MSPS Analog-To-Digital Converter
中文描述: 11位,125 MSPS的模擬到數(shù)字轉(zhuǎn)換器
文件頁(yè)數(shù): 24/29頁(yè)
文件大小: 835K
代理商: ADS5510
www.ti.com
ADS5510
SLAS499–JANUARY 2007
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positive
overdrive, the output code is 0x7FF in straight offset binary output format and 0x3FF in two's complement output
format. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x400
in two's complement output format. These outputs to an overdrive signal are ensured through design and
characterization.
The output circuitry of the ADS5510, by design, minimizes the noise produced by the data switching transients,
and, in particular, its coupling to the ADC analog circuitry. Output D1 (pin 51) senses the load capacitance and
adjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described in
the timing diagram of
Figure 1
. Care should be taken to ensure that all output lines (including CLKOUT) have
nearly the same load as D1 (pin 51). This circuit also reduces the sensitivity of the output timing versus supply
voltage or temperature. Placing external resistors in series with the outputs is
not
recommended.
The timing characteristics of the digital outputs change for sampling rates below the 125 MSPS maximum
sampling frequency.
Table 5
and
Table 6
show the setup, hold, input clock to output data delays, and rise and
fall times for different sampling frequencies with the DLL on and off, respectively.
Table 7
and
Table 8
show the rise and fall times at additional sampling frequencies with DLL on and off,
respectively.
To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, t
d
, that
results in the desired setup or hold time. Use either
Equation 2
or
Equation 3
to calculate the value of t
d
.
Desired setup time = t
d
– t
START
Desired hold time = t
END
– t
d
Table 5. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
t
SETUP
(ns)
MIN
TYP
2.4
3.2
2.8
3.8
t
HOLD
(ns)
TYP
2.6
3.7
3.3
4.1
t
START
(ns)
MIN
TYP
t
END
(ns)
TYP
7.3
t
r
(ns)
TYP
4.4
t
f
(ns)
TYP
3.3
f
(MSPS)
MAX
MIN
2.2
2.3
2.8
3.6
MAX
MAX
2.6
MIN
5.8
MAX
MIN
MAX
5.1
MIN
MAX
3.8
105
93
80
65
3.1
4.6
3.7
4.6
1.7
0.5
–0.5
1.7
0.8
5.3
5.3
7.9
8.5
5.8
6.7
6.6
7.2
4.4
5.5
5.3
6.4
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
t
SETUP
(ns)
MIN
TYP
3.2
4.3
8.5
17
25.7
27
284
t
HOLD
(ns)
TYP
3
3
3.5
4.7
6.5
19
t
START
(ns)
MIN
TYP
t
END
(ns)
TYP
11
11.8
14.5
21.6
31
576
t
r
(ns)
TYP
5.8
6.6
7.5
7.5
t
f
(ns)
TYP
4.4
5.5
7.3
7.6
f
(MSPS)
MAX
MIN
1.8
2
2.6
2.5
4
8
MAX
MAX
5
4.5
1.5
2
-3
320
MIN
8.4
8.3
8.9
9.5
11.5
515
MAX
MIN
MAX
6.6
7.2
8
8
MIN
MAX
5.3
6.4
7.8
8
80
65
40
20
10
2
4.2
5.7
11
3.8
2.8
–1
–9.8
-30
185
51
370
50
82
75
150
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
CLKOUT Jitter,
Peak-to-Peak
t
JIT
(ps)
TYP
175
210
260
CLKOUT, Rise Time
t
r
(ns)
CLKOUT, Fall Time
t
f
(ns)
Input-to-Output Clock Delay
t
PDI
(ns)
f
(MSPS)
MIN
TYP
2
2.5
3.1
MAX
2.2
2.8
3.5
MIN
TYP
1.7
2.1
2.6
MAX
1.8
2.3
2.9
MIN
MAX
250
315
380
MIN
4
3.7
3.5
TYP
4.7
4.3
4.1
MAX
5.5
5.1
4.8
105
80
65
24
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