參數(shù)資料
型號: ADS62P44IRGCRG4
廠商: Texas Instruments
文件頁數(shù): 6/78頁
文件大?。?/td> 0K
描述: IC ADC 14BIT SER/PAR 105M 64VQFN
產品培訓模塊: Data Converter Basics
標準包裝: 2,000
位數(shù): 14
采樣率(每秒): 105M
數(shù)據(jù)接口: 串行,并聯(lián)
轉換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤
供應商設備封裝: 64-VQFN 裸露焊盤(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個差分,單極
SLAS561C
– JULY 2007 – REVISED FEBRUARY 2012
DETAILS OF PARALLEL CONFIGURATION ONLY
The functions controlled by each parallel pin are described below. A simple way of configuring the parallel pins is
shown in Figure 5.
Table 4. SCLK (Analog Control Pin)
VOLTAGE APPLIED ON SCLK
DESCRIPTION
0
0dB gain and Internal reference
+200mV/-0mV
(3/8)AVDD
0dB gain and External reference
+/- 200mV
(5/8)2AVDD
3.5dB Coarse gain and External reference
+/- 200mV
AVDD
3.5dB Coarse gain and Internal reference
+0mV/-200mV
Table 5. SEN (Analog Control Pin)
VOLTAGE APPLIED ON SEN
DESCRIPTION
0
2s complement format and DDR LVDS output
+200mV/-0mV
(3/8)AVDD
Straight binary and DDR LVDS output
+/- 200mV
(5/8)AVDD
Straight binary and parallel CMOS output
+/- 200mV
AVDD
2s complement format and parallel CMOS output
+0mV/-200mV
Table 6. CTRL1, CTRL2 and CTRL3 (Digital Control Pins)
CTRL1
CTRL2
CTRL3
DESCRIPTION
LOW
Normal operation
LOW
HIGH
Channel A output buffer disabled
LOW
HIGH
LOW
Channel B output buffer disabled
LOW
HIGH
Channel A and B output buffer disabled
HIGH
LOW
Power down global
HIGH
LOW
HIGH
Channel A standby
HIGH
LOW
Channel B standby
MUX mode of operation (only with CMOS interface Channel A and B data is multiplexed and
HIGH
output on DB13 to DB0 pins. See Multiplexed output mode for detailed description.
14
Copyright
2007–2012, Texas Instruments Incorporated
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