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參數(shù)資料
| 型號： | ADS7616A4A-7 |
| 廠商： | ADATA Technology Co., Ltd. |
| 英文描述： | Synchronous DRAM(2M X 16 Bit X 4 Banks) |
| 中文描述： | 同步DRAM（2米× 16位× 4個銀行） |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 565K |
| 代理商： | ADS7616A4A-7 |
A-Data
ADS7616A4A
AC Characteristics
Speed
-5.5
-6
-7
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Note
/CAS Latency = 3 tCK3
5.5
6
7
System clock
Cycle time
/CAS Latency = 2 tCK2
7.5
1000
7.5
1000
7.5
1000
ns
Clock high pulse width
tCHW
2
-
2
-
2.5
-
ns
1
Clock low pulse width
tCLW
2
-
2
-
2.5
-
ns
1
/CAS Latency = 3 tAC3
-
5
-
5
-
5.4
Access time form
clock
/CAS Latency = 2 tAC2
-
5.4
-
5.4
-
5.4
ns
2
/RAS cycle time Operation
tRC
57
-
57
-
57
--
ns
/RAS to /CAS delay
tRCD
15
-
15
-
15
-
ns
/RAS active time
tRAS
42
100K
42
100K
42
100K
ns
/RAS precharge time
tRP
15
-
15
-
15
-
ns
/CAS to /CAS delay
tCCD
1
-
1
-
1
-
CLK
DQM to data – in mask
tDQM
0
-
0
-
0
-
CLK
Data – out hold time
tOH
2.75
-
2.75
-
3
-
ns
Data – input setup time
tDS
1.5
-
1.5
-
1.5
-
ns
1
Data – input hold time
tDH
0.8
-
0.8
-
0.8
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
ns
1
Address hold time
tAH
0.8
-
0.8
-
0.8
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
ns
1
CKE hold time
tCKH
0.8
-
0.8
-
0.8
-
ns
1
Command setup time
tCMS
1.5
-
1.5
-
1.5
-
ns
1
Command hold time
tCMH
0.8
-
0.8
-
0.8
-
ns
1
CLK to data output in low Z-time
tOLZ
1
-
1
-
1
-
ns
MRS to new command
tMRD
1
-
1
-
2
-
CLK
Power down exit time
tPDE
1
-
1
-
1
-
CLK
Self refresh exit time
tSRE
1
-
1
-
1
-
CLK
3
Refresh time
tREF
-
64
64
64
ms
Note :
1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.0 April, 2001
6
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